riscv/rocket-chip
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Don't drive D$ kill/phys signals for SimpleHellaCacheIF

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They don't do anything.
This commit is contained in:
Andrew Waterman 2016-04-01 19:31:54 -07:00
parent 6d3bba6cff
commit 7285f5e6bf
4 changed files with 0 additions and 10 deletions
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4
groundtest/src/main/scala/dmatest.scala
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@ -97,8 +97,6 @@ class DmaStreamTest(implicit p: Parameters) extends GroundTest()(p)
io.cache.req.bits.data := test_data(req_index) io.cache.req.bits.data := test_data(req_index)
io.cache.req.bits.typ := UInt(log2Up(conf.size)) io.cache.req.bits.typ := UInt(log2Up(conf.size))
io.cache.req.bits.cmd := Mux(state === s_setup_req, M_XWR, M_XRD) io.cache.req.bits.cmd := Mux(state === s_setup_req, M_XWR, M_XRD)
io.cache.req.bits.kill := Bool(false)
io.cache.req.bits.phys := Bool(false)
when (state === s_start) { state := s_setup_req } when (state === s_start) { state := s_setup_req }
when (state === s_setup_req && req_done) { state := s_setup_wait } when (state === s_setup_req && req_done) { state := s_setup_wait }
@ -173,8 +171,6 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
io.cache.req.bits.data := req_data io.cache.req.bits.data := req_data
io.cache.req.bits.typ := MT_W io.cache.req.bits.typ := MT_W
io.cache.req.bits.cmd := Mux(state === s_fill_req, M_XWR, M_XRD) io.cache.req.bits.cmd := Mux(state === s_fill_req, M_XWR, M_XRD)
io.cache.req.bits.kill := Bool(false)
io.cache.req.bits.phys := Bool(false)
when (state === s_start) { when (state === s_start) {
req_addr := sourceAddrs(testIdx) req_addr := sourceAddrs(testIdx)

2
groundtest/src/main/scala/generator.scala
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@ -162,8 +162,6 @@ class HellaCacheGenerator(id: Int)
io.mem.req.bits.typ := MT_D io.mem.req.bits.typ := MT_D
io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD) io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
io.mem.req.bits.tag := UInt(0) io.mem.req.bits.tag := UInt(0)
io.mem.req.bits.kill := Bool(false)
io.mem.req.bits.phys := Bool(true)
when (state === s_start) { sending := Bool(true); state := s_write } when (state === s_start) { sending := Bool(true); state := s_write }

2
groundtest/src/main/scala/regression.scala
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@ -53,8 +53,6 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.cache.req.bits.typ := MT_W io.cache.req.bits.typ := MT_W
io.cache.req.bits.cmd := M_XRD io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0) io.cache.req.bits.tag := UInt(0)
io.cache.req.bits.kill := Bool(false)
io.cache.req.bits.phys := Bool(true)
when (put_done) { put_sent := Bool(true) } when (put_done) { put_sent := Bool(true) }
when (io.cache.req.fire()) { get_sent := Bool(true) } when (io.cache.req.fire()) { get_sent := Bool(true) }

2
groundtest/src/main/scala/tracegen.scala
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@ -470,8 +470,6 @@ class TraceGenerator(id: Int)
io.mem.req.bits.typ := MT_D io.mem.req.bits.typ := MT_D
io.mem.req.bits.cmd := reqCmd io.mem.req.bits.cmd := reqCmd
io.mem.req.bits.tag := reqTag io.mem.req.bits.tag := reqTag
io.mem.req.bits.kill := Bool(false)
io.mem.req.bits.phys := Bool(true)
// On cycle when request is actually sent, print it // On cycle when request is actually sent, print it
when (io.mem.req.fire()) { when (io.mem.req.fire()) {