riscv/rocket-chip
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Take a stab at the PRCI-Rocket interface

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This commit is contained in:
Andrew Waterman 2016-05-02 15:19:43 -07:00
parent 695c4c5096
commit 72731de25a
2 changed files with 25 additions and 1 deletions
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1
uncore/src/main/scala/htif.scala
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@ -44,7 +44,6 @@ class HostIO(w: Int) extends Bundle {
class HtifIO(implicit p: Parameters) extends HtifBundle()(p) { class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
val reset = Bool(INPUT) val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(nCores)) val id = UInt(INPUT, log2Up(nCores))
val timerIRQ = Bool(INPUT)
val csr = new SmiIO(csrDataBits, 12).flip val csr = new SmiIO(csrDataBits, 12).flip
} }

25
uncore/src/main/scala/prci.scala Normal file
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@ -0,0 +1,25 @@
// See LICENSE for license details.
package uncore
import Chisel._
import Chisel.ImplicitConversions._
import junctions._
import junctions.NastiConstants._
import cde.{Parameters, Field}
/** Number of tiles */
case object NTiles extends Field[Int]
class PRCICoreIO(implicit p: Parameters) extends Bundle {
val reset = Bool(OUTPUT)
val id = UInt(OUTPUT, log2Up(p(NTiles)))
val interrupts = new Bundle {
val mtip = Bool()
val msip = Bool()
val meip = Bool()
val seip = Bool()
}.asOutput
override def cloneType: this.type = new PRCICoreIO().asInstanceOf[this.type]
}