From 72731de25a6e53f41446a0d1bece875aa97e475a Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 2 May 2016 15:19:43 -0700
Subject: [PATCH] Take a stab at the PRCI-Rocket interface

---
 uncore/src/main/scala/htif.scala |  1 -
 uncore/src/main/scala/prci.scala | 25 +++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)
 create mode 100644 uncore/src/main/scala/prci.scala

diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala
index e13bdcbc..5ffffd11 100644
--- a/uncore/src/main/scala/htif.scala
+++ b/uncore/src/main/scala/htif.scala
@@ -44,7 +44,6 @@ class HostIO(w: Int) extends Bundle {
 class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
   val reset = Bool(INPUT)
   val id = UInt(INPUT, log2Up(nCores))
-  val timerIRQ = Bool(INPUT)
   val csr = new SmiIO(csrDataBits, 12).flip
 }
 
diff --git a/uncore/src/main/scala/prci.scala b/uncore/src/main/scala/prci.scala
new file mode 100644
index 00000000..c66fbde3
--- /dev/null
+++ b/uncore/src/main/scala/prci.scala
@@ -0,0 +1,25 @@
+// See LICENSE for license details.
+
+package uncore
+
+import Chisel._
+import Chisel.ImplicitConversions._
+import junctions._
+import junctions.NastiConstants._
+import cde.{Parameters, Field}
+
+/** Number of tiles */
+case object NTiles extends Field[Int]
+
+class PRCICoreIO(implicit p: Parameters) extends Bundle {
+  val reset = Bool(OUTPUT)
+  val id = UInt(OUTPUT, log2Up(p(NTiles)))
+  val interrupts = new Bundle {
+    val mtip = Bool()
+    val msip = Bool()
+    val meip = Bool()
+    val seip = Bool()
+  }.asOutput
+
+  override def cloneType: this.type = new PRCICoreIO().asInstanceOf[this.type]
+}