riscv/rocket-chip
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new htif protocol and implementation

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You must update your fesvr and isasim!
This commit is contained in:
Andrew Waterman
2012-02-19 23:15:45 -08:00
parent 9af86633d7
commit 7034c9be65
8 changed files with 242 additions and 95 deletions
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22
rocket/src/main/scala/cpu.scala
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@ -10,25 +10,10 @@ class ioDebug(view: List[String] = null) extends Bundle(view)
val error_mode = Bool(OUTPUT);
}
class ioHost(view: List[String] = null) extends Bundle(view)
{
val from_wen = Bool(INPUT);
val from = Bits(64, INPUT);
val to = Bits(64, OUTPUT);
}
class ioConsole(view: List[String] = null) extends Bundle(view)
{
val rdy = Bool(INPUT);
val valid = Bool(OUTPUT);
val bits = Bits(8, OUTPUT);
}
class ioRocket extends Bundle()
{
val debug = new ioDebug();
val console = new ioConsole();
val host = new ioHost();
val host = new ioHTIF();
val imem = new ioImem().flip();
val vimem = new ioImem().flip();
val dmem = new ioDmem().flip();
@ -47,6 +32,7 @@ class rocketProc extends Component
val ptw = new rocketPTW();
val arb = new rocketDmemArbiter();
ctrl.io.htif_reset := io.host.reset
ctrl.io.dpath <> dpath.io.ctrl;
dpath.io.host <> io.host;
dpath.io.debug <> io.debug;
@ -112,10 +98,6 @@ class rocketProc extends Component
dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
dpath.io.dmem.resp_data_subword := io.dmem.resp_data_subword;
io.console.bits := dpath.io.console.bits;
io.console.valid := dpath.io.console.valid;
ctrl.io.console.rdy := io.console.rdy;
if (HAVE_FPU)
{
val fpu = new rocketFPU(4,6)