new htif protocol and implementation

You must update your fesvr and isasim!
2012-02-19 23:15:45 -08:00
parent 9af86633d7
commit 7034c9be65
8 changed files with 242 additions and 95 deletions
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@ -138,7 +138,6 @@ object Constants
  val PCR_TOHOST   = UFix(16, 5);
  val PCR_FROMHOST = UFix(17, 5);
  val PCR_VECBANK  = UFix(18, 5);
-  val PCR_CONSOLE  = UFix(19, 5);

  // definition of bits in PCR status reg
  val SR_ET   = 0;  // enable traps