riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

new htif protocol and implementation

Browse Source 
You must update your fesvr and isasim!
This commit is contained in:
Andrew Waterman committed 2012-02-19 23:15:45 -08:00
1 parent 9af86633d7
commit 7034c9be65
8 files changed
+242 -95
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

rocket/src/main/scala/consts.scala
-1
View File
@@ -138,7 +138,6 @@ object Constants
val PCR_TOHOST = UFix(16, 5);
val PCR_FROMHOST = UFix(17, 5);
val PCR_VECBANK = UFix(18, 5);
val PCR_CONSOLE = UFix(19, 5);
// definition of bits in PCR status reg
val SR_ET = 0; // enable traps