Merge pull request #55 from ucb-bar/travis-regression

travis-ci.org improvements
2016-02-23 12:19:59 -08:00 · 2016-02-23 12:19:59 -08:00 · 700d756de0
commit 700d756de0
parent 0ac5c07683 bae4c0c0c9
5 changed files with 70 additions and 69 deletions
--- a/.travis.yml
+++ b/.travis.yml
@ -1,7 +1,12 @@
 language: scala
 # run on new infrastructure
 sudo: false
-cache: apt
+cache:
+  apt: true
+  directories:
+    $HOME/.ivy2
+    regression/install
+
 # packages needed to build riscv-tools
 addons:
  apt:
@ -24,17 +29,14 @@ addons:
      - texinfo

 env:
-  global:
-    - RISCV="/home/travis/riscv_install"
-    - PATH=$PATH:$RISCV/bin
  matrix:
-    - VCONFIG=DefaultVLSIConfig FCONFIG=DefaultFPGAConfig ECONFIG=DefaultCPPConfig
-    - VCONFIG=RoccExampleConfig FCONFIG=RoccExampleConfig ECONFIG=RoccExampleConfig
-    - VCONFIG=DmaControllerConfig FCONFIG=DmaControllerFPGAConfig ECONFIG=DmaControllerConfig
-    - VCONFIG=MemtestConfig FCONFIG=MemtestConfig ECONFIG=MemtestConfig
-    - VCONFIG=MemtestL2Config FCONFIG=MemtestL2Config ECONFIG=MemtestL2Config
-    - VCONFIG=BroadcastRegressionTestConfig FCONFIG=BroadcastRegressionTestConfig ECONFIG=BroadcastRegressionTestConfig
-    - VCONFIG=CacheRegressionTestConfig FCONFIG=CacheRegressionTestConfig ECONFIG=CacheRegressionTestConfig
+    - CONFIG=DefaultCPPConfig
+    - CONFIG=RoccExampleConfig
+    - CONFIG=DmaControllerConfig
+    - CONFIG=MemtestConfig
+    - CONFIG=MemtestL2Config
+    - CONFIG=BroadcastRegressionTestConfig
+    - CONFIG=CacheRegressionTestConfig

 # blacklist private branches
 branches:
@ -44,41 +46,15 @@ branches:
    - hurricane

 before_install:
-  # make install destination
-  - mkdir -p $RISCV
-  # don't do travis on riscv-tools
  - rm riscv-tools/.travis.yml
-  # pull in needed repos from riscv-tools (travis isn't recursive)
-  - cd riscv-tools
-  - git submodule update --init riscv-fesvr
-  - git submodule update --init riscv-gnu-toolchain
-  - git submodule update --init riscv-tests
-  - cd riscv-tests
-  - git submodule update --init
-  - cd ../..
-  # use recently installed gcc
  - export CXX=g++-4.8 CC=gcc-4.8

 script:
-  # test verilog
-  - cd vsim
-  - make CONFIG=$VCONFIG verilog
-  - cd ../fsim
-  - make CONFIG=$FCONFIG verilog
-  # build riscv-fesvr
-  - cd ../riscv-tools/riscv-fesvr
-  - mkdir build
-  - cd build
-  - ../configure --prefix=$RISCV
-  - make install
-  # build emulator
-  - cd ../../../emulator
-  - make -j 8 CONFIG=$ECONFIG
-  # build riscv-gcc
-  - cd ../riscv-tools/riscv-gnu-toolchain
-  - ./configure --prefix=$RISCV
-  - make -j 8 > build.gcc.out
-  # run riscv-tests
-  - cd ../../emulator
-  - make -j 8 CONFIG=$ECONFIG run-asm-tests
-  - make CONFIG=$ECONFIG run-bmark-tests
+  - make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
+  - make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
+  - make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
+  - make emulator-asm-tests   -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
+  - make emulator-bmark-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default -j1
+
+before_cache:
+  - ls -tr regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf
--- a/regression/Makefile
+++ b/regression/Makefile
@ -19,8 +19,12 @@ endif
 # The top-level directory that contains rocket-chip
 TOP ?= ..

+# The hash of the tools that we're using
+TOOLS_HASH ?= $(shell git -C $(TOP) ls-tree HEAD -- riscv-tools | xargs echo | cut -d' ' -f3)
+$(info Using riscv-tools of $(TOOLS_HASH))
+
 # The directory that the tools get built into.
-RISCV ?= install
+RISCV ?= install/$(TOOLS_HASH)

 # Torture saves the failing tests into a directory, which defaults to just somehing inside the regressions directory.
 TORTURE_SAVE_DIR ?= torture-failures
@ -37,8 +41,8 @@ clean:
 # this order, since there's dependencies for everything it doesn't actually
 # matter.  They're here to make running the various targets from the
 # commandline a bit cleaner.
-submodules: stamps/submodules.stamp
-tools: stamps/tools.stamp
+submodules: stamps/other-submodules.stamp
+tools: $(RISCV)/install.stamp

 emulator-debug: stamps/$(CONFIG)/emulator-debug.stamp
 emulator-ndebug: stamps/$(CONFIG)/emulator-ndebug.stamp
@ -46,12 +50,14 @@ emulator-asm-tests: stamps/$(CONFIG)/emulator-asm-tests.stamp
 emulator-bmark-tests: stamps/$(CONFIG)/emulator-bmark-tests.stamp
 emulator-torture: stamps/$(CONFIG)/emulator-torture-$(TORTURE_CONFIG).stamp

+vsim-verilog: stamps/$(CONFIG)/vsim-verilog.stamp
 vsim-debug: stamps/$(CONFIG)/vsim-debug.stamp
 vsim-ndebug: stamps/$(CONFIG)/vsim-ndebug.stamp
 vsim-asm-tests: stamps/$(CONFIG)/vsim-asm-tests.stamp
 vsim-bmark-tests: stamps/$(CONFIG)/vsim-bmark-tests.stamp
 vsim-torture: stamps/$(CONFIG)/vsim-torture-$(TORTURE_CONFIG).stamp

+fsim-verilog: stamps/$(CONFIG)/fsim-verilog.stamp
 fsim-debug: stamps/$(CONFIG)/fsim-debug.stamp
 fsim-ndebug: stamps/$(CONFIG)/fsim-ndebug.stamp
 fsim-asm-tests: stamps/$(CONFIG)/fsim-asm-tests.stamp
@ -59,47 +65,66 @@ fsim-bmark-tests: stamps/$(CONFIG)/fsim-bmark-tests.stamp
 fsim-torture: stamps/$(CONFIG)/fsim-torture-$(TORTURE_CONFIG).stamp

 # Checks out all the rocket-chip submodules
-stamps/submodules.stamp:
+stamps/other-submodules.stamp:
 	mkdir -p $(dir $@)
-	git -C $(abspath $(TOP)) submodule update --init --recursive
-	touch $@
+	git -C $(abspath $(TOP)) submodule update --init --recursive chisel
+	git -C $(abspath $(TOP)) submodule update --init --recursive context-dependent-environments
+	git -C $(abspath $(TOP)) submodule update --init --recursive dramsim2
+	git -C $(abspath $(TOP)) submodule update --init --recursive groundtest
+	git -C $(abspath $(TOP)) submodule update --init --recursive hardfloat
+	git -C $(abspath $(TOP)) submodule update --init --recursive junctions
+	git -C $(abspath $(TOP)) submodule update --init --recursive rocket
+	git -C $(abspath $(TOP)) submodule update --init --recursive torture
+	git -C $(abspath $(TOP)) submodule update --init --recursive uncore
+	date > $@

-# Builds the RISC-V toolchain
-stamps/tools.stamp: stamps/submodules.stamp
+$(RISCV)/install.stamp:
 	mkdir -p $(dir $@)
+	git -C $(abspath $(TOP)) submodule update --init riscv-tools
+	git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-gnu-toolchain
+	git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-isa-sim
+	git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-fesvr
+	git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-opcodes
+	git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-pk
+	git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-tests
 	+cd $(abspath $(TOP))/riscv-tools; RISCV=$(abspath $(RISCV)) ./build.sh
-	touch $@
+	date > $@

 # Builds the various simulators
-stamps/$(CONFIG)/%-ndebug.stamp: stamps/submodules.stamp stamps/tools.stamp
+stamps/$(CONFIG)/%-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
+	mkdir -p $(dir $@)
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-verilog.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) verilog
+	date > $@	
+
+stamps/$(CONFIG)/%-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
 	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-ndebug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV))
-	touch $@
+	date > $@

-stamps/$(CONFIG)/%-debug.stamp: stamps/submodules.stamp stamps/tools.stamp
+stamps/$(CONFIG)/%-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
 	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-debug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) debug
-	touch $@
+	date > $@

 # Runs tests on one of the simulators
-stamps/$(CONFIG)/%-asm-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp stamps/tools.stamp stamps/submodules.stamp
+stamps/$(CONFIG)/%-asm-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp
 	mkdir -p $(dir $@)
 	$(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-asm-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) run-asm-tests
-	touch $@
+	date > $@

-stamps/$(CONFIG)/%-bmark-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp stamps/tools.stamp stamps/submodules.stamp
+stamps/$(CONFIG)/%-bmark-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp
 	mkdir -p $(dir $@)
 	$(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-bmark-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) run-bmark-tests
-	touch $@
+	date > $@

 # The torture tests run subtly differently on the different targets, so they
 # don't have pattern rules like everything else does.
 stamps/$(CONFIG)/vsim-torture-$(TORTURE_CONFIG).stamp: stamps/$(CONFIG)/vsim-debug.stamp stamps/$(CONFIG)/vsim-ndebug.stamp
 	mkdir -p $(dir $@)
 	$(MAKE) -C $(abspath $(TOP))/torture rnight RTL_CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10"
-	touch $@
+	date > $@

-stamps/$(CONFIG)/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/$(CONFIG)/emulator-debug.stamp stamps/$(CONFIG)/emulator-ndebug.stamp
+stamps/$(CONFIG)/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/$(CONFIG)/emulator-debug.stamp stamps/$(CONFIG)/emulator-debug.stamp
 	mkdir -p $(dir $@)
 	$(MAKE) -C $(abspath $(TOP))/torture cnight RTL_CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) PATH="$(abspath $(RISCV)/bin:$(PATH))" OPTIONS="-C $(abspath $(TOP)/torture/config/$(TORTURE_CONFIG).config) -p $(abspath $(TORTURE_SAVE_DIR)) -m 30 -t 10"
-	touch $@
+	date > $@
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 2065218d0a8c25ea721f8036d9098eb91a31920c
+Subproject commit 509c745061ce072e175015b9df83310a68eeb4a4
--- a/src/main/scala/Testing.scala
+++ b/src/main/scala/Testing.scala
@ -147,10 +147,10 @@ object DefaultTestSuites {
  val rv64u = List(rv64ui, rv64um, rv64ua)
  val rv64i = List(rv64ui, rv64si, rv64mi)

-  val bmarks = new BenchmarkTestSuite("basic", "$(base_dir)/riscv-tools/riscv-tests/benchmarks", LinkedHashSet(
+  val bmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
    "median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul"))

-  val mtBmarks = new BenchmarkTestSuite("mt", "$(base_dir)/riscv-tools/riscv-tests/mt",
+  val mtBmarks = new BenchmarkTestSuite("mt", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/mt",
    LinkedHashSet(((0 to 4).map("vvadd"+_) ++
    List("ad","ae","af","ag","ai","ak","al","am","an","ap","aq","ar","at","av","ay","az",
         "bb","bc","bf","bh","bj","bk","bm","bo","br","bs","ce","cf","cg","ci","ck","cl",
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 733342509b271bffb3b6df51b85784abc6627ad8
+Subproject commit b54b3d0d80cd620ddcce1680201c6f366051d150