From 888f6a2a5551ee15dc97ee1d77756de6420c7284 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 15 Sep 2016 11:48:09 -0700
Subject: [PATCH 01/13] Revert "move UnitTest back into rocketchip module"

This reverts commit f95b8c4ec2bcde5cb7a1df18b99906e446d3ddb9.
---
 regression/Makefile                      | 33 +++++++++++-------------
 src/main/scala/rocketchip/UnitTest.scala |  4 +--
 2 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/regression/Makefile b/regression/Makefile
index 7d222c4f..ca210738 100644
--- a/regression/Makefile
+++ b/regression/Makefile
@@ -39,13 +39,11 @@ $(error Set SUITE to the regression suite you want to run)
 endif
 
 ifeq ($(SUITE),RocketSuite)
-MODEL=TestHarness
 PROJECT=rocketchip
 CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig
 endif
 
 ifeq ($(SUITE),GroundtestSuite)
-MODEL=TestHarness
 PROJECT=rocketchip
 CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
 	BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
@@ -53,8 +51,7 @@ CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtes
 endif
 
 ifeq ($(SUITE),UnittestSuite)
-MODEL=UnitTestHarness
-PROJECT=rocketchip
+PROJECT=rocketchip.utest
 CONFIGS=UnitTestConfig
 endif
 
@@ -126,65 +123,65 @@ $(RISCV)/install.stamp:
 # Builds the various simulators
 stamps/%/emulator-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
 	date > $@
 
 stamps/%/emulator-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV))
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
 	date > $@
 
 stamps/%/emulator-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
 	date > $@
 
 stamps/%/vsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
 	date > $@
 
 stamps/%/vsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV))
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
 	date > $@
 
 stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
 	date > $@
 
 # Runs tests on one of the simulators
 stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
 	date > $@
 
 stamps/%/emulator-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
 	date > $@
 
 stamps/%/emulator-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
-	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
+	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
 	date > $@
 
 stamps/%/vsim-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
 	date > $@
 
 stamps/%/vsim-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
 	date > $@
 
 stamps/%/vsim-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
-	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
+	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
 	date > $@
 
 # The torture tests run subtly differently on the different targets, so they
diff --git a/src/main/scala/rocketchip/UnitTest.scala b/src/main/scala/rocketchip/UnitTest.scala
index 1d23e3c7..d310caac 100644
--- a/src/main/scala/rocketchip/UnitTest.scala
+++ b/src/main/scala/rocketchip/UnitTest.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package rocketchip
+package rocketchip.utest
 
 import scala.collection.mutable.LinkedHashSet
 
@@ -31,7 +31,7 @@ class WithUnitTest extends Config(
 
 class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
 
-class UnitTestHarness(implicit val p: Parameters) extends Module {
+class TestHarness(implicit val p: Parameters) extends Module {
   val io = new Bundle {
     val success = Bool(OUTPUT)
   }

From 9e2b0aad65f2b7d3a126f90711577988573ddc4a Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 15 Sep 2016 11:53:05 -0700
Subject: [PATCH 02/13] Revert "allow MODEL to be something other than
 TestHarness"

This reverts commit bf253aaa972964e68e1ac04d12de240bb7ee57df.
---
 csrc/emulator.cc            | 2 +-
 emulator/Makefrag-verilator | 2 +-
 vsim/Makefrag               | 1 -
 vsrc/TestDriver.v           | 2 +-
 4 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index af6e0ac0..db914704 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -65,7 +65,7 @@ int main(int argc, char** argv)
   srand48(random_seed);
 
   Verilated::randReset(2);
-  MODEL *tile = new MODEL;
+  VTestHarness *tile = new VTestHarness;
 
 #if VM_TRACE
   Verilated::traceEverOn(true); // Verilator must compute traced signals
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index 2e4435cb..2cf13f33 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -54,7 +54,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
   +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
 	-Wno-STMTDLY --x-assign unique \
   -I$(base_dir)/vsrc \
-  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h -DMODEL=V$(MODEL)"
+  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
 cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
 headers = $(wildcard $(base_dir)/csrc/*.h)
 
diff --git a/vsim/Makefrag b/vsim/Makefrag
index ba537d85..31ee449b 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -51,7 +51,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
 	+incdir+$(generated_dir) \
-	+define+MODEL=$(MODEL) \
 	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \
diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index 305593c0..4d5bd632 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -87,7 +87,7 @@ module TestDriver;
     end
   end
 
-  `MODEL testHarness(
+  TestHarness testHarness(
     .clk(clk),
     .reset(reset),
     .io_success(success)

From c6f252a9136eb789f16a0daae18bdf266268fef9 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 15 Sep 2016 12:19:22 -0700
Subject: [PATCH 03/13] Remove Option from success flag in coreplex; just use a
 sane default.

---
 src/main/scala/coreplex/Coreplex.scala      | 9 +++++----
 src/main/scala/rocketchip/TestHarness.scala | 4 ++--
 src/main/scala/rocketchip/Top.scala         | 4 ++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala
index 2da93f9f..619f6410 100644
--- a/src/main/scala/coreplex/Coreplex.scala
+++ b/src/main/scala/coreplex/Coreplex.scala
@@ -57,14 +57,16 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
     val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
     val debug = new DebugBusIO()(p).flip
     val prci = Vec(c.nTiles, new PRCITileIO).flip
-    val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
+    val success = Bool(OUTPUT)
   }
 
-  def hasSuccessFlag: Boolean = false
   val io = new CoreplexIO
 }
 
 class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
+  // Coreplex doesn't know when to stop running
+  io.success := Bool(false)
+
   // Build a set of Tiles
   val tileResets = Wire(Vec(tc.nTiles, Bool()))
   val tileList = p(BuildTiles).zip(tileResets).map {
@@ -164,6 +166,5 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
 }
 
 class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
-  override def hasSuccessFlag = true
-  io.success.get := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
+  io.success := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
 }
diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index 9e073499..7b7dd239 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -136,12 +136,12 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
   }
 
   def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.DebugBusIO,
-      dutsuccess: Option[Bool], tbsuccess: Bool) = {
+      dutsuccess: Bool, tbsuccess: Bool) = {
     io.clk := tbclk
     io.reset := tbreset
     dutio <> io.debug
 
-    tbsuccess := dutsuccess.getOrElse(io.exit === 1)
+    tbsuccess := dutsuccess || io.exit === 1
     when (io.exit >= 2) {
       printf("*** FAILED *** (exit code = %d)\n", io.exit >> 1)
       stop(1)
diff --git a/src/main/scala/rocketchip/Top.scala b/src/main/scala/rocketchip/Top.scala
index c56ffc46..46610458 100644
--- a/src/main/scala/rocketchip/Top.scala
+++ b/src/main/scala/rocketchip/Top.scala
@@ -29,7 +29,7 @@ abstract class BaseTop(val p: Parameters) extends LazyModule {
 }
 
 class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
-  val success = c.hasSuccessFlag.option(Bool(OUTPUT))
+  val success = Bool(OUTPUT)
 }
 
 class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
@@ -65,7 +65,7 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
   val coreplex = p(BuildCoreplex)(p, c)
   val io: B = b(coreplex)
 
-  io.success zip coreplex.io.success map { case (x, y) => x := y }
+  io.success := coreplex.io.success
 
   val mmioNetwork = c.hasExtMMIOPort.option(
     Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(

From be9ddae77f9038cf9b582c418ae37100c692bc52 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 15 Sep 2016 13:04:01 -0700
Subject: [PATCH 04/13] make groundtest and unitest peers of rocketchip, with
 their own packages, harnesses and configs

---
 regression/Makefile                           |   4 +-
 src/main/scala/coreplex/Configs.scala         |   9 +-
 src/main/scala/coreplex/Coreplex.scala        |   4 -
 .../Configs.scala}                            | 124 ++++++++++++++++-
 src/main/scala/groundtest/Coreplex.scala      |   9 ++
 src/main/scala/groundtest/TestHarness.scala   |   7 +
 src/main/scala/rocketchip/TestConfigs.scala   | 127 ------------------
 .../UnitTest.scala => unittest/Configs.scala} |   4 +-
 src/main/scala/util/ConfigUtils.scala         |  11 ++
 9 files changed, 151 insertions(+), 148 deletions(-)
 rename src/main/scala/{coreplex/TestConfigs.scala => groundtest/Configs.scala} (55%)
 create mode 100644 src/main/scala/groundtest/Coreplex.scala
 create mode 100644 src/main/scala/groundtest/TestHarness.scala
 delete mode 100644 src/main/scala/rocketchip/TestConfigs.scala
 rename src/main/scala/{rocketchip/UnitTest.scala => unittest/Configs.scala} (93%)
 create mode 100644 src/main/scala/util/ConfigUtils.scala

diff --git a/regression/Makefile b/regression/Makefile
index ca210738..95a23319 100644
--- a/regression/Makefile
+++ b/regression/Makefile
@@ -44,14 +44,14 @@ CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig
 endif
 
 ifeq ($(SUITE),GroundtestSuite)
-PROJECT=rocketchip
+PROJECT=groundtest
 CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
 	BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
 	ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig
 endif
 
 ifeq ($(SUITE),UnittestSuite)
-PROJECT=rocketchip.utest
+PROJECT=unittest
 CONFIGS=UnitTestConfig
 endif
 
diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 8d8d87ad..14604529 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -11,19 +11,12 @@ import uncore.devices._
 import uncore.converters._
 import rocket._
 import rocket.Util._
+import util.ConfigUtils._
 import rocketchip.{GlobalAddrMap, NCoreplexExtClients}
-import scala.math.max
 import scala.collection.mutable.{LinkedHashSet, ListBuffer}
 import DefaultTestSuites._
 import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
 
-object ConfigUtils {
-  def max_int(values: Int*): Int = {
-    values.reduce((a, b) => max(a, b))
-  }
-}
-import ConfigUtils._
-
 class BaseCoreplexConfig extends Config (
   topDefinitions = { (pname,site,here) => 
     type PF = PartialFunction[Any,Any]
diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala
index 619f6410..1c6ef1b9 100644
--- a/src/main/scala/coreplex/Coreplex.scala
+++ b/src/main/scala/coreplex/Coreplex.scala
@@ -164,7 +164,3 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
     io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
   }
 }
-
-class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
-  io.success := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
-}
diff --git a/src/main/scala/coreplex/TestConfigs.scala b/src/main/scala/groundtest/Configs.scala
similarity index 55%
rename from src/main/scala/coreplex/TestConfigs.scala
rename to src/main/scala/groundtest/Configs.scala
index b2e7e05c..d7db98f2 100644
--- a/src/main/scala/coreplex/TestConfigs.scala
+++ b/src/main/scala/groundtest/Configs.scala
@@ -1,19 +1,133 @@
-package coreplex
+package groundtest
 
 import Chisel._
-import groundtest._
-import rocketchip.{GlobalAddrMap}
 import rocket._
 import uncore.tilelink._
 import uncore.coherence._
 import uncore.agents._
 import uncore.devices.NTiles
-import unittest._
 import junctions._
 import scala.collection.mutable.LinkedHashSet
+import scala.collection.immutable.HashMap
 import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
 import scala.math.max
-import ConfigUtils._
+import coreplex._
+import rocketchip._
+import util.ConfigUtils._
+
+/** Actual testing target Configs */
+
+class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
+
+class ComparatorConfig extends Config(
+  new WithComparator ++ new GroundTestConfig)
+class ComparatorL2Config extends Config(
+  new WithAtomics ++ new WithPrefetches ++
+  new WithL2Cache ++ new ComparatorConfig)
+class ComparatorBufferlessConfig extends Config(
+  new WithBufferlessBroadcastHub ++ new ComparatorConfig)
+class ComparatorStatelessConfig extends Config(
+  new WithStatelessBridge ++ new ComparatorConfig)
+
+class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
+class MemtestL2Config extends Config(
+  new WithL2Cache ++ new MemtestConfig)
+class MemtestBufferlessConfig extends Config(
+  new WithBufferlessBroadcastHub ++ new MemtestConfig)
+class MemtestStatelessConfig extends Config(
+  new WithNGenerators(0, 1) ++ new WithStatelessBridge ++ new MemtestConfig)
+// Test ALL the things
+class FancyMemtestConfig extends Config(
+  new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++
+  new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
+  new WithSplitL2Metadata ++ new WithL2Cache ++ new GroundTestConfig)
+
+class CacheFillTestConfig extends Config(
+  new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig)
+
+class BroadcastRegressionTestConfig extends Config(
+  new WithBroadcastRegressionTest ++ new GroundTestConfig)
+class BufferlessRegressionTestConfig extends Config(
+  new WithBufferlessBroadcastHub ++ new BroadcastRegressionTestConfig)
+class CacheRegressionTestConfig extends Config(
+  new WithCacheRegressionTest ++ new WithL2Cache ++ new GroundTestConfig)
+
+class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
+class FancyNastiConverterTestConfig extends Config(
+  new WithNCores(2) ++ new WithNastiConverterTest ++
+  new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
+  new WithL2Cache ++ new GroundTestConfig)
+
+class TraceGenConfig extends Config(
+  new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)
+class TraceGenBufferlessConfig extends Config(
+  new WithBufferlessBroadcastHub ++ new TraceGenConfig)
+class TraceGenL2Config extends Config(
+  new WithNL2Ways(1) ++ new WithL2Capacity(32 * 64 / 1024) ++
+  new WithL2Cache ++ new TraceGenConfig)
+
+class MIF128BitComparatorConfig extends Config(
+  new WithMIFDataBits(128) ++ new ComparatorConfig)
+class MIF128BitMemtestConfig extends Config(
+  new WithMIFDataBits(128) ++ new MemtestConfig)
+
+class MIF32BitComparatorConfig extends Config(
+  new WithMIFDataBits(32) ++ new ComparatorConfig)
+class MIF32BitMemtestConfig extends Config(
+  new WithMIFDataBits(32) ++ new MemtestConfig)
+
+class PCIeMockupTestConfig extends Config(
+  new WithPCIeMockupTest ++ new GroundTestConfig)
+
+/* Composable Configs to set individual parameters */
+class WithGroundTest extends Config(
+  (pname, site, here) => pname match {
+    case BuildCoreplex =>
+      (p: Parameters, c: CoreplexConfig) => Module(new GroundTestCoreplex(p, c))
+    case TLKey("L1toL2") => {
+      val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
+      TileLinkParameters(
+        coherencePolicy = (
+          if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
+          else new MESICoherence(site(L2DirectoryRepresentation))),
+        nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
+        nCachingClients = site(NCachedTileLinkPorts),
+        nCachelessClients = site(NCoreplexExtClients).get + site(NUncachedTileLinkPorts),
+        maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
+                           site(GroundTestKey).map(_.maxXacts))
+                             .reduce(max(_, _)),
+        maxClientsPerPort = 1,
+        maxManagerXacts = site(NAcquireTransactors) + 2,
+        dataBeats = 8,
+        dataBits = site(CacheBlockBytes)*8)
+    }
+    case BuildTiles => {
+      val groundtest = if (site(XLen) == 64)
+        DefaultTestSuites.groundtest64
+      else
+        DefaultTestSuites.groundtest32
+      TestGeneration.addSuite(groundtest("p"))
+      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
+      (0 until site(NTiles)).map { i =>
+        val tileSettings = site(GroundTestKey)(i)
+        (r: Bool, p: Parameters) => {
+          Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
+            case TLId => "L1toL2"
+            case TileId => i
+            case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
+            case NUncachedTileLinkPorts => tileSettings.uncached
+          })))
+        }
+      }
+    }
+    case BuildExampleTop =>
+      (p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTopWithTestRAM(p))
+    case FPUKey => None
+    case UseAtomics => false
+    case UseCompressed => false
+    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
+    case _ => throw new CDEMatchError
+  })
 
 class WithComparator extends Config(
   (pname, site, here) => pname match {
diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala
new file mode 100644
index 00000000..2d93ee42
--- /dev/null
+++ b/src/main/scala/groundtest/Coreplex.scala
@@ -0,0 +1,9 @@
+package groundtest
+
+import Chisel._
+import cde.{Parameters}
+import coreplex.{CoreplexConfig, DefaultCoreplex}
+
+class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
+  io.success := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
+}
diff --git a/src/main/scala/groundtest/TestHarness.scala b/src/main/scala/groundtest/TestHarness.scala
new file mode 100644
index 00000000..8853c513
--- /dev/null
+++ b/src/main/scala/groundtest/TestHarness.scala
@@ -0,0 +1,7 @@
+package groundtest
+
+import Chisel._
+import cde.Parameters
+
+// !!! TODO: Replace with a groundtest-specific test harness
+class TestHarness(implicit p: Parameters) extends rocketchip.TestHarness()(p)
diff --git a/src/main/scala/rocketchip/TestConfigs.scala b/src/main/scala/rocketchip/TestConfigs.scala
deleted file mode 100644
index 96127f16..00000000
--- a/src/main/scala/rocketchip/TestConfigs.scala
+++ /dev/null
@@ -1,127 +0,0 @@
-package rocketchip
-
-import Chisel._
-import groundtest._
-import rocket._
-import uncore.tilelink._
-import uncore.coherence._
-import uncore.agents._
-import uncore.devices.NTiles
-import junctions._
-import scala.collection.mutable.LinkedHashSet
-import scala.collection.immutable.HashMap
-import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
-import scala.math.max
-import coreplex._
-import ConfigUtils._
-
-class WithGroundTest extends Config(
-  (pname, site, here) => pname match {
-    case BuildCoreplex =>
-      (p: Parameters, c: CoreplexConfig) => Module(new GroundTestCoreplex(p, c))
-    case TLKey("L1toL2") => {
-      val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
-      TileLinkParameters(
-        coherencePolicy = (
-          if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
-          else new MESICoherence(site(L2DirectoryRepresentation))),
-        nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
-        nCachingClients = site(NCachedTileLinkPorts),
-        nCachelessClients = site(NCoreplexExtClients).get + site(NUncachedTileLinkPorts),
-        maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
-                           site(GroundTestKey).map(_.maxXacts))
-                             .reduce(max(_, _)),
-        maxClientsPerPort = 1,
-        maxManagerXacts = site(NAcquireTransactors) + 2,
-        dataBeats = 8,
-        dataBits = site(CacheBlockBytes)*8)
-    }
-    case BuildTiles => {
-      val groundtest = if (site(XLen) == 64)
-        DefaultTestSuites.groundtest64
-      else
-        DefaultTestSuites.groundtest32
-      TestGeneration.addSuite(groundtest("p"))
-      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
-      (0 until site(NTiles)).map { i =>
-        val tileSettings = site(GroundTestKey)(i)
-        (r: Bool, p: Parameters) => {
-          Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
-            case TLId => "L1toL2"
-            case TileId => i
-            case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
-            case NUncachedTileLinkPorts => tileSettings.uncached
-          })))
-        }
-      }
-    }
-    case BuildExampleTop =>
-      (p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTopWithTestRAM(p))
-    case FPUKey => None
-    case UseAtomics => false
-    case UseCompressed => false
-    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
-    case _ => throw new CDEMatchError
-  })
-
-class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
-
-class ComparatorConfig extends Config(
-  new WithComparator ++ new GroundTestConfig)
-class ComparatorL2Config extends Config(
-  new WithAtomics ++ new WithPrefetches ++
-  new WithL2Cache ++ new ComparatorConfig)
-class ComparatorBufferlessConfig extends Config(
-  new WithBufferlessBroadcastHub ++ new ComparatorConfig)
-class ComparatorStatelessConfig extends Config(
-  new WithStatelessBridge ++ new ComparatorConfig)
-
-class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
-class MemtestL2Config extends Config(
-  new WithL2Cache ++ new MemtestConfig)
-class MemtestBufferlessConfig extends Config(
-  new WithBufferlessBroadcastHub ++ new MemtestConfig)
-class MemtestStatelessConfig extends Config(
-  new WithNGenerators(0, 1) ++ new WithStatelessBridge ++ new MemtestConfig)
-// Test ALL the things
-class FancyMemtestConfig extends Config(
-  new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++
-  new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
-  new WithSplitL2Metadata ++ new WithL2Cache ++ new GroundTestConfig)
-
-class CacheFillTestConfig extends Config(
-  new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig)
-
-class BroadcastRegressionTestConfig extends Config(
-  new WithBroadcastRegressionTest ++ new GroundTestConfig)
-class BufferlessRegressionTestConfig extends Config(
-  new WithBufferlessBroadcastHub ++ new BroadcastRegressionTestConfig)
-class CacheRegressionTestConfig extends Config(
-  new WithCacheRegressionTest ++ new WithL2Cache ++ new GroundTestConfig)
-
-class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
-class FancyNastiConverterTestConfig extends Config(
-  new WithNCores(2) ++ new WithNastiConverterTest ++
-  new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
-  new WithL2Cache ++ new GroundTestConfig)
-
-class TraceGenConfig extends Config(
-  new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)
-class TraceGenBufferlessConfig extends Config(
-  new WithBufferlessBroadcastHub ++ new TraceGenConfig)
-class TraceGenL2Config extends Config(
-  new WithNL2Ways(1) ++ new WithL2Capacity(32 * 64 / 1024) ++
-  new WithL2Cache ++ new TraceGenConfig)
-
-class MIF128BitComparatorConfig extends Config(
-  new WithMIFDataBits(128) ++ new ComparatorConfig)
-class MIF128BitMemtestConfig extends Config(
-  new WithMIFDataBits(128) ++ new MemtestConfig)
-
-class MIF32BitComparatorConfig extends Config(
-  new WithMIFDataBits(32) ++ new ComparatorConfig)
-class MIF32BitMemtestConfig extends Config(
-  new WithMIFDataBits(32) ++ new MemtestConfig)
-
-class PCIeMockupTestConfig extends Config(
-  new WithPCIeMockupTest ++ new GroundTestConfig)
diff --git a/src/main/scala/rocketchip/UnitTest.scala b/src/main/scala/unittest/Configs.scala
similarity index 93%
rename from src/main/scala/rocketchip/UnitTest.scala
rename to src/main/scala/unittest/Configs.scala
index d310caac..5a891c6a 100644
--- a/src/main/scala/rocketchip/UnitTest.scala
+++ b/src/main/scala/unittest/Configs.scala
@@ -1,11 +1,11 @@
 // See LICENSE for license details.
 
-package rocketchip.utest
+package unittest
 
 import scala.collection.mutable.LinkedHashSet
 
 import Chisel._
-import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import cde.{Parameters, Config, Knob, CDEMatchError}
 import util.{ParameterizedBundle}
 import rocket._
 import uncore.tilelink._
diff --git a/src/main/scala/util/ConfigUtils.scala b/src/main/scala/util/ConfigUtils.scala
new file mode 100644
index 00000000..4e5cd8f0
--- /dev/null
+++ b/src/main/scala/util/ConfigUtils.scala
@@ -0,0 +1,11 @@
+// See LICENSE for license details.
+
+package util
+
+import scala.math.max
+
+object ConfigUtils {
+  def max_int(values: Int*): Int = {
+    values.reduce((a, b) => max(a, b))
+  }
+}

From 245f8ab76b11e25318f7a12201271704a0b37e73 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 15 Sep 2016 13:30:34 -0700
Subject: [PATCH 05/13] [util] move LatencyPipe into util

---
 src/main/scala/rocketchip/TestHarness.scala | 21 +----------------
 src/main/scala/util/LatencyPipe.scala       | 25 +++++++++++++++++++++
 2 files changed, 26 insertions(+), 20 deletions(-)
 create mode 100644 src/main/scala/util/LatencyPipe.scala

diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index 7b7dd239..33a26444 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -5,6 +5,7 @@ package rocketchip
 import Chisel._
 import cde.{Parameters, Field}
 import rocket.Util._
+import util.LatencyPipe
 import junctions._
 import junctions.NastiConstants._
 
@@ -175,23 +176,3 @@ class JTAGVPI(implicit val p: Parameters) extends BlackBox {
     tbsuccess := Bool(false)
   }
 }
-
-class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {
-  val io = new Bundle {
-    val in = Decoupled(typ).flip
-    val out = Decoupled(typ)
-  }
-
-  def doN[T](n: Int, func: T => T, in: T): T =
-    (0 until n).foldLeft(in)((last, _) => func(last))
-
-  io.out <> doN(latency, (last: DecoupledIO[T]) => Queue(last, 1, pipe=true), io.in)
-}
-
-object LatencyPipe {
-  def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] = {
-    val pipe = Module(new LatencyPipe(in.bits, latency))
-    pipe.io.in <> in
-    pipe.io.out
-  }
-}
diff --git a/src/main/scala/util/LatencyPipe.scala b/src/main/scala/util/LatencyPipe.scala
new file mode 100644
index 00000000..b629bef8
--- /dev/null
+++ b/src/main/scala/util/LatencyPipe.scala
@@ -0,0 +1,25 @@
+// See LICENSE for license details.
+
+package util
+
+import Chisel._
+
+class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {
+  val io = new Bundle {
+    val in = Decoupled(typ).flip
+    val out = Decoupled(typ)
+  }
+
+  def doN[T](n: Int, func: T => T, in: T): T =
+    (0 until n).foldLeft(in)((last, _) => func(last))
+
+  io.out <> doN(latency, (last: DecoupledIO[T]) => Queue(last, 1, pipe=true), io.in)
+}
+
+object LatencyPipe {
+  def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] = {
+    val pipe = Module(new LatencyPipe(in.bits, latency))
+    pipe.io.in <> in
+    pipe.io.out
+  }
+}

From 851a336db4322ac06bc7427a1e715f7ce5066277 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 15 Sep 2016 14:25:47 -0700
Subject: [PATCH 06/13] [unittest] split out Config and TestHarness into
 separate files, minimize imports

---
 src/main/scala/unittest/Configs.scala     | 29 +++--------------------
 src/main/scala/unittest/TestHarness.scala | 21 ++++++++++++++++
 2 files changed, 24 insertions(+), 26 deletions(-)
 create mode 100644 src/main/scala/unittest/TestHarness.scala

diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala
index 5a891c6a..4d5c628e 100644
--- a/src/main/scala/unittest/Configs.scala
+++ b/src/main/scala/unittest/Configs.scala
@@ -5,42 +5,19 @@ package unittest
 import scala.collection.mutable.LinkedHashSet
 
 import Chisel._
-import cde.{Parameters, Config, Knob, CDEMatchError}
-import util.{ParameterizedBundle}
-import rocket._
-import uncore.tilelink._
-import uncore.tilelink2.{LazyModule, LazyModuleImp}
+import cde.{Parameters, Config, CDEMatchError}
 import coreplex._
 import rocketchip._
-import unittest._
 
 class WithUnitTest extends Config(
   (pname, site, here) => pname match {
     case UnitTests => (testParams: Parameters) => {
-      val groundtest = if (site(XLen) == 64)
-        DefaultTestSuites.groundtest64
-      else
-        DefaultTestSuites.groundtest32
-      TestGeneration.addSuite(groundtest("p"))
+      TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
       TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
-      JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
+      JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams) // TODO refactor
     }
     case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
     case _ => throw new CDEMatchError
   })
 
 class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
-
-class TestHarness(implicit val p: Parameters) extends Module {
-  val io = new Bundle {
-    val success = Bool(OUTPUT)
-  }
-
-  p(NCoreplexExtClients).assign(0)
-  p(ConfigString).assign("")
-
-  val l1params = p.alterPartial({ case TLId => "L1toL2" })
-  val tests = Module(new UnitTestSuite()(l1params))
-
-  io.success := tests.io.finished
-}
diff --git a/src/main/scala/unittest/TestHarness.scala b/src/main/scala/unittest/TestHarness.scala
new file mode 100644
index 00000000..a394e431
--- /dev/null
+++ b/src/main/scala/unittest/TestHarness.scala
@@ -0,0 +1,21 @@
+// See LICENSE for license details.
+
+package unittest
+
+import Chisel._
+import cde.Parameters
+import rocketchip._
+
+class TestHarness(implicit val p: Parameters) extends Module {
+  val io = new Bundle {
+    val success = Bool(OUTPUT)
+  }
+
+  p(NCoreplexExtClients).assign(0)
+  p(ConfigString).assign("")
+
+  val l1params = p.alterPartial({ case uncore.tilelink.TLId => "L1toL2" })
+  val tests = Module(new UnitTestSuite()(l1params))
+
+  io.success := tests.io.finished
+}

From 3fdf40c088805b0a7bce0bfac4a77e065a4ee5f9 Mon Sep 17 00:00:00 2001
From: Richard Xia <rxia@sifive.com>
Date: Fri, 16 Sep 2016 17:47:31 -0700
Subject: [PATCH 07/13] Change implicit argument to explicit.

---
 src/main/scala/groundtest/TestHarness.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/groundtest/TestHarness.scala b/src/main/scala/groundtest/TestHarness.scala
index 8853c513..dbabf0da 100644
--- a/src/main/scala/groundtest/TestHarness.scala
+++ b/src/main/scala/groundtest/TestHarness.scala
@@ -4,4 +4,4 @@ import Chisel._
 import cde.Parameters
 
 // !!! TODO: Replace with a groundtest-specific test harness
-class TestHarness(implicit p: Parameters) extends rocketchip.TestHarness()(p)
+class TestHarness(implicit p: Parameters) extends rocketchip.TestHarness(p)

From 7b8aa6c83960cb6eb67635b0113b8515b5a1cac1 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Mon, 19 Sep 2016 11:00:13 -0700
Subject: [PATCH 08/13] [rocketchip] split out Base and Example tops

---
 .../rocketchip/{Top.scala => BaseTop.scala}   | 27 --------------
 src/main/scala/rocketchip/ExampleTop.scala    | 35 +++++++++++++++++++
 2 files changed, 35 insertions(+), 27 deletions(-)
 rename src/main/scala/rocketchip/{Top.scala => BaseTop.scala} (63%)
 create mode 100644 src/main/scala/rocketchip/ExampleTop.scala

diff --git a/src/main/scala/rocketchip/Top.scala b/src/main/scala/rocketchip/BaseTop.scala
similarity index 63%
rename from src/main/scala/rocketchip/Top.scala
rename to src/main/scala/rocketchip/BaseTop.scala
index f467eee2..58cec5b6 100644
--- a/src/main/scala/rocketchip/Top.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -81,30 +81,3 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
   println(p(ConfigString))
   ConfigStringOutput.contents = Some(p(ConfigString))
 }
-
-/** Example Top with Periphery */
-class ExampleTop(q: Parameters) extends BaseTop(q)
-    with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
-    with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
-  override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
-}
-
-class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
-    with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
-    with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
-
-class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
-    with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
-    with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
-
-/** Example Top with TestRAM */
-class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
-    with PeripheryTestRAM {
-  override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
-}
-
-class ExampleTopWithTestRAMBundle(p: Parameters, c: Coreplex) extends ExampleTopBundle(p, c)
-    with PeripheryTestRAMBundle
-
-class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: Coreplex => B) extends ExampleTopModule(p, l, b)
-    with PeripheryTestRAMModule
diff --git a/src/main/scala/rocketchip/ExampleTop.scala b/src/main/scala/rocketchip/ExampleTop.scala
new file mode 100644
index 00000000..3895273d
--- /dev/null
+++ b/src/main/scala/rocketchip/ExampleTop.scala
@@ -0,0 +1,35 @@
+// See LICENSE for license details.
+
+package rocketchip
+
+import Chisel._
+import cde.{Parameters, Field}
+import coreplex.Coreplex
+import rocketchip._
+
+/** Example Top with Periphery */
+class ExampleTop(q: Parameters) extends BaseTop(q)
+    with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
+    with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
+  override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
+}
+
+class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
+    with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
+    with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
+
+class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
+    with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
+    with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
+
+/** Example Top with TestRAM */
+class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
+    with PeripheryTestRAM {
+  override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
+}
+
+class ExampleTopWithTestRAMBundle(p: Parameters, c: Coreplex) extends ExampleTopBundle(p, c)
+    with PeripheryTestRAMBundle
+
+class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: Coreplex => B) extends ExampleTopModule(p, l, b)
+    with PeripheryTestRAMModule

From ddcf1b4099b801a096cf6657f047bf63fe2fc440 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Mon, 19 Sep 2016 13:23:17 -0700
Subject: [PATCH 09/13] Use PROJECT rather than MODEL in name of binary and
 generated src files.

---
 Makefrag                                  |  8 ++++--
 emulator/Makefile                         |  5 +---
 emulator/Makefrag-verilator               | 31 +++++++++++------------
 src/main/scala/rocketchip/Generator.scala |  2 +-
 vsim/Makefile                             |  3 +--
 vsim/Makefrag-verilog                     | 18 ++++++-------
 6 files changed, 33 insertions(+), 34 deletions(-)

diff --git a/Makefrag b/Makefrag
index a3ff6e37..e76bb737 100644
--- a/Makefrag
+++ b/Makefrag
@@ -6,6 +6,10 @@ endif
 MODEL ?= TestHarness
 PROJECT ?= rocketchip
 CFG_PROJECT ?= $(PROJECT)
+CONFIG ?= DefaultConfig
+# TODO: For now must match rocketchip.Generator
+long_name = $(PROJECT).$(CONFIG)
+
 CXX ?= g++
 CXXFLAGS := -O1
 
@@ -50,7 +54,7 @@ bootrom_img = $(base_dir)/bootrom/bootrom.img
 #---------------------------------------------------------------------
 
 # sed uses -E (instead of -r) for BSD support
-params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm
+params_file = $(generated_dir)/$(long_name).prm
 consts_header = $(generated_dir)/consts.$(CONFIG).h
 $(consts_header): $(params_file)
 	echo "#ifndef __CONST_H__" > $@
@@ -58,7 +62,7 @@ $(consts_header): $(params_file)
 	sed -E 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
 	echo "#endif // __CONST_H__" >> $@
 
-params_file_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).prm
+params_file_debug = $(generated_dir_debug)/$(long_name).prm
 consts_header_debug = $(generated_dir_debug)/consts.$(CONFIG).h
 $(consts_header_debug): $(params_file_debug)
 	echo "#ifndef __CONST_H__" > $@
diff --git a/emulator/Makefile b/emulator/Makefile
index eb0b881b..32ee7b60 100644
--- a/emulator/Makefile
+++ b/emulator/Makefile
@@ -6,9 +6,6 @@ generated_dir_debug = $(abspath ./generated-src-debug)
 sim_dir = .
 output_dir = $(sim_dir)/output
 
-BACKEND = c
-CONFIG ?= DefaultConfig
-
 include $(base_dir)/Makefrag
 
 CXXSRCS := emulator SimDTM
@@ -36,7 +33,7 @@ test:
 #--------------------------------------------------------------------
 
 ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
--include $(generated_dir)/$(MODEL).$(CONFIG).d
+-include $(generated_dir)/$(long_name).d
 endif
 
 $(output_dir)/%.run: $(output_dir)/% $(emu)
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index 2cf13f33..1767f15b 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -1,19 +1,18 @@
 #--------------------------------------------------------------------
 # Verilator Generation 
 #--------------------------------------------------------------------
-
-firrtl = $(generated_dir)/$(MODEL).$(CONFIG).fir
-firrtl_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
-verilog = $(generated_dir)/$(MODEL).$(CONFIG).v
-verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
+firrtl = $(generated_dir)/$(long_name).fir
+firrtl_debug = $(generated_dir_debug)/$(long_name).fir
+verilog = $(generated_dir)/$(long_name).v
+verilog_debug = $(generated_dir_debug)/$(long_name).v
 
 .SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
 
-$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
+$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
 	cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
-$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs) $(bootrom_img)
+$(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug)/%.d: $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
 	cd $(base_dir) && $(SBT) "run $(generated_dir_debug) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
@@ -58,19 +57,19 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
 cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
 headers = $(wildcard $(base_dir)/csrc/*.h)
 
-model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
-model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG)/V$(MODEL).h
+model_header = $(generated_dir)/$(long_name)/V$(MODEL).h
+model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
 
 $(emu): $(verilog) $(cppfiles) $(headers) $(consts_header) $(INSTALLED_VERILATOR)
-	mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
-	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
+	mkdir -p $(generated_dir)/$(long_name)
+	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
 	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
-	$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
+	$(MAKE) -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
 
-$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
-	mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
-	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG)  --trace \
+$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) $(consts_header_debug) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
+	mkdir -p $(generated_dir_debug)/$(long_name)
+	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name)  --trace \
 	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)"
-	$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
+	$(MAKE) -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk
diff --git a/src/main/scala/rocketchip/Generator.scala b/src/main/scala/rocketchip/Generator.scala
index f4f24247..669da10a 100644
--- a/src/main/scala/rocketchip/Generator.scala
+++ b/src/main/scala/rocketchip/Generator.scala
@@ -77,7 +77,7 @@ trait Generator extends App with HasGeneratorUtilities {
   lazy val world = config.toInstance
   lazy val params = Parameters.root(world)
   lazy val circuit = elaborate(names, params)
-  lazy val longName = names.topModuleClass + "." + names.configs
+  lazy val longName = names.topProject + "." + names.configs
 
   def writeOutputFiles() {
     TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
diff --git a/vsim/Makefile b/vsim/Makefile
index 7d4ea481..769a4c3f 100644
--- a/vsim/Makefile
+++ b/vsim/Makefile
@@ -17,13 +17,12 @@ sim_dir = .
 output_dir = $(sim_dir)/output
 
 BACKEND ?= v
-CONFIG ?= DefaultConfig
 TB ?= TestDriver
 
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag
 ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
--include $(generated_dir)/$(MODEL).$(CONFIG).d
+-include $(generated_dir)/$(long_name).d
 endif
 include $(base_dir)/vsim/Makefrag-verilog
 
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index 00785e33..c0ab9576 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -3,27 +3,27 @@
 #--------------------------------------------------------------------
 # If I don't mark these as .SECONDARY then make will delete these internal
 # files.
-.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
+.SECONDARY: $(generated_dir)/$(long_name).fir
 
-firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
+firrtl: $(generated_dir)/$(long_name).fir
 
 .PHONY: firrtl
 
-$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
+$(generated_dir)/%.fir $(generated_dir)/%.d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
-	cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"
+	cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
-$(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR)
+$(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf
+	$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
 
-$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen)
+$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
 	cd $(generated_dir) && \
 	rm -f $@ && \
-	$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $@.tmp && \
+	$(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
 	mv $@.tmp $@
 
-$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
+$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(long_name).prm
 	echo "\`ifndef CONST_VH" > $@
 	echo "\`define CONST_VH" >> $@
 	sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@

From df442ed82c4e42db787de5b4ee1a53ce0b8bd908 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Mon, 19 Sep 2016 13:24:01 -0700
Subject: [PATCH 10/13] [rocketchip] avoid pending merge conflict]

---
 src/main/scala/rocketchip/BaseTop.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 58cec5b6..31785603 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -61,8 +61,6 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
   val coreplex = p(BuildCoreplex)(p, outer.c)
   val io: B = b(coreplex)
 
-  io.success := coreplex.io.success
-
   val mmioNetwork =
     Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
       p.alterPartial({ case TLId => "L2toMMIO" })))
@@ -80,4 +78,6 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
   println("Generated Configuration String")
   println(p(ConfigString))
   ConfigStringOutput.contents = Some(p(ConfigString))
+
+  io.success := coreplex.io.success
 }

From 2961d92244f17ccd6be35ab2884ed82cc1ff3292 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Mon, 19 Sep 2016 13:46:45 -0700
Subject: [PATCH 11/13] [testharness] vsim makefrag cleanup

---
 vsim/Makefrag         |  8 ++++----
 vsim/Makefrag-verilog | 13 ++++++-------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/vsim/Makefrag b/vsim/Makefrag
index f06fc032..36606737 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -15,8 +15,8 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
 
 
 sim_vsrcs = \
-	$(generated_dir)/$(MODEL).$(CONFIG).v \
-	$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v \
+	$(generated_dir)/$(long_name).v \
+	$(generated_dir)/$(long_name).behav_srams.v \
 	$(generated_dir)/consts.$(CONFIG).vh \
 	$(base_dir)/vsrc/$(TB).v \
 	$(base_dir)/vsrc/SimDTM.v \
@@ -70,14 +70,14 @@ VCS_OPTS += -CC "-DVCS_VPI"
 # Build the simulator
 #--------------------------------------------------------------------
 
-simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
+simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
 $(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
 	cd $(sim_dir) && \
 	rm -rf csrc && \
 	$(VCS) $(VCS_OPTS) -o $(simv) \
 	-debug_pp \
 
-simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
+simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
 $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
 	cd $(sim_dir) && \
 	rm -rf csrc && \
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index c0ab9576..12fb7678 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -1,21 +1,20 @@
 #--------------------------------------------------------------------
 # Verilog Generation
 #--------------------------------------------------------------------
+firrtl = $(generated_dir)/$(long_name).fir
+verilog = $(generated_dir)/$(long_name).v
+
 # If I don't mark these as .SECONDARY then make will delete these internal
 # files.
-.SECONDARY: $(generated_dir)/$(long_name).fir
+.SECONDARY: $(firrtl) $(verilog)
 
-firrtl: $(generated_dir)/$(long_name).fir
-
-.PHONY: firrtl
-
-$(generated_dir)/%.fir $(generated_dir)/%.d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
+$(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
 	cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
 $(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
+	$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
 
 $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
 	cd $(generated_dir) && \

From b97a0947a9f7143eb23d141f8600c96272af3d20 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Tue, 20 Sep 2016 12:57:56 -0700
Subject: [PATCH 12/13] [rocketchip] enable piecewise Generator output

---
 src/main/scala/rocketchip/Generator.scala | 58 ++++++++++++++++++-----
 1 file changed, 45 insertions(+), 13 deletions(-)

diff --git a/src/main/scala/rocketchip/Generator.scala b/src/main/scala/rocketchip/Generator.scala
index 669da10a..04c47db7 100644
--- a/src/main/scala/rocketchip/Generator.scala
+++ b/src/main/scala/rocketchip/Generator.scala
@@ -8,17 +8,21 @@ import cde._
 import coreplex._
 import java.io.{File, FileWriter}
 
+/** Representation of the information this Generator needs to collect from external sources. */
 case class ParsedInputNames(
     targetDir: String,
-    topProject: String,
+    topModuleProject: String,
     topModuleClass: String,
     configProject: String,
     configs: String) {
   val configClasses: Seq[String] = configs.split('_')
   val fullConfigClasses: Seq[String] = configClasses.map(configProject + "." + _)
-  val fullTopModuleClass: String = topProject + "." + topModuleClass
+  val fullTopModuleClass: String = topModuleProject + "." + topModuleClass
 }
 
+/** Common utilities we supply to all Generators. In particular, supplies the
+  * canonical ways of building various JVM elaboration-time structures.
+  */
 trait HasGeneratorUtilities {
   def getConfig(names: ParsedInputNames): Config = {
     names.fullConfigClasses.foldRight(new Config()) { case (currentName, config) =>
@@ -56,40 +60,68 @@ trait HasGeneratorUtilities {
   }
 }
 
-object ConfigStringOutput {
-  var contents: Option[String] = None
-}
 
+/** Standardized command line interface for Scala entry point */
 trait Generator extends App with HasGeneratorUtilities {
-  lazy val names = {
+  lazy val names: ParsedInputNames = {
     require(args.size == 5, "Usage: sbt> " + 
       "run TargetDir TopModuleProjectName TopModuleName ConfigProjectName ConfigNameString")
     ParsedInputNames(
       targetDir = args(0),
-      topProject = args(1),
+      topModuleProject = args(1),
       topModuleClass = args(2),
       configProject = args(3),
       configs = args(4))
   }
 
+  // Canonical ways of building various JVM elaboration-time structures
   lazy val td = names.targetDir
   lazy val config = getConfig(names)
   lazy val world = config.toInstance
   lazy val params = Parameters.root(world)
   lazy val circuit = elaborate(names, params)
-  lazy val longName = names.topProject + "." + names.configs
 
-  def writeOutputFiles() {
+  val longName: String // Exhaustive name used to interface with external build tool targets
+
+  /** Output FIRRTL, which an external compiler can turn into Verilog. */
+  def generateFirrtl {
+    Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
+  }
+
+  /** Output software test Makefrags, which provide targets for integration testing. */
+  def generateTestSuiteMakefrags {
     TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
     writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites
-    writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
+  }
+
+  /** Output Design Space Exploration knobs and constraints. */
+  def generateDSEConstraints {
     writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
     writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
+  }
+
+  /** Output a global Parameter dump, which an external script can turn into Verilog headers. */
+  def generateParameterDump {
+    writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
+  }
+
+  /** Output a global ConfigString, for use by the RISC-V software ecosystem. */
+  def generateConfigString {
     ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c)) // String for software
   }
 }
 
-object RocketChipGenerator extends Generator {
-  Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
-  writeOutputFiles()
+object ConfigStringOutput {
+  var contents: Option[String] = None
+}
+
+/** An example Generator */
+object RocketChipGenerator extends Generator
+{
+  val longName = names.topModuleProject + "." + names.configs
+  generateFirrtl
+  generateTestSuiteMakefrags
+  generateDSEConstraints
+  generateConfigString
+  generateParameterDump
 }

From 40f6f3161134fafac57e5929673b8a3ec70c21a1 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Tue, 20 Sep 2016 14:14:30 -0700
Subject: [PATCH 13/13] [unittest] further refactor unittest framework

---
 src/main/scala/unittest/Configs.scala         | 31 ++++++++++++++++---
 src/main/scala/unittest/TempListOfTests.scala | 20 ------------
 src/main/scala/unittest/TestHarness.scala     | 17 ++--------
 src/main/scala/unittest/UnitTest.scala        |  3 +-
 4 files changed, 31 insertions(+), 40 deletions(-)
 delete mode 100644 src/main/scala/unittest/TempListOfTests.scala

diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala
index 4d5c628e..8daac49e 100644
--- a/src/main/scala/unittest/Configs.scala
+++ b/src/main/scala/unittest/Configs.scala
@@ -9,15 +9,36 @@ import cde.{Parameters, Config, CDEMatchError}
 import coreplex._
 import rocketchip._
 
-class WithUnitTest extends Config(
+class WithJunctionsUnitTests extends Config(
   (pname, site, here) => pname match {
-    case UnitTests => (testParams: Parameters) => {
+    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
+    case UnitTests => (p: Parameters) => {
       TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
       TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
-      JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams) // TODO refactor
+      Seq(
+        Module(new junctions.MultiWidthFifoTest),
+        Module(new junctions.NastiMemoryDemuxTest()(p)),
+        Module(new junctions.HastiTest()(p)))
     }
-    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
+    case UnitTestTimeout => 50000
     case _ => throw new CDEMatchError
   })
 
-class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
+class WithUncoreUnitTests extends Config(
+  (pname, site, here) => pname match {
+    case NCoreplexExtClients => 0
+    case uncore.tilelink.TLId => "L1toL2"
+    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
+    case UnitTests => (p: Parameters) => {
+      TestGeneration.addSuite(DefaultTestSuites.groundtest64("p")) // TODO why
+      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
+      Seq(
+        Module(new uncore.devices.ROMSlaveTest()(p)),
+        Module(new uncore.devices.TileLinkRAMTest()(p)),
+        Module(new uncore.tilelink2.TLFuzzRAMTest))
+    }
+    case UnitTestTimeout => 500000
+    case _ => throw new CDEMatchError
+  })
+
+class UnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithJunctionsUnitTests ++ new BaseConfig)
diff --git a/src/main/scala/unittest/TempListOfTests.scala b/src/main/scala/unittest/TempListOfTests.scala
deleted file mode 100644
index d770943a..00000000
--- a/src/main/scala/unittest/TempListOfTests.scala
+++ /dev/null
@@ -1,20 +0,0 @@
-package unittest
-
-import Chisel._
-import cde.Parameters
-
-object JunctionsUnitTests {
-  def apply(implicit p: Parameters): Seq[UnitTest] =
-    Seq(
-      Module(new junctions.MultiWidthFifoTest),
-      Module(new junctions.NastiMemoryDemuxTest),
-      Module(new junctions.HastiTest))
-}
-
-object UncoreUnitTests {
-  def apply(implicit p: Parameters): Seq[UnitTest] =
-    Seq(
-      Module(new uncore.devices.ROMSlaveTest),
-      Module(new uncore.devices.TileLinkRAMTest),
-      Module(new uncore.tilelink2.TLFuzzRAMTest))
-}
diff --git a/src/main/scala/unittest/TestHarness.scala b/src/main/scala/unittest/TestHarness.scala
index d689c876..8ddc1364 100644
--- a/src/main/scala/unittest/TestHarness.scala
+++ b/src/main/scala/unittest/TestHarness.scala
@@ -3,19 +3,8 @@
 package unittest
 
 import Chisel._
-import cde.Parameters
-import rocketchip._
 
-class TestHarness(implicit val p: Parameters) extends Module {
-  val io = new Bundle {
-    val success = Bool(OUTPUT)
-  }
-
-  val l1params = p.alterPartial({
-    case NCoreplexExtClients => 0
-    case ConfigString => ""
-    case uncore.tilelink.TLId => "L1toL2" })
-  val tests = Module(new UnitTestSuite()(l1params))
-
-  io.success := tests.io.finished
+class TestHarness(implicit val p: cde.Parameters) extends Module {
+  val io = new Bundle { val success = Bool(OUTPUT) }
+  io.success := Module(new UnitTestSuite).io.finished
 }
diff --git a/src/main/scala/unittest/UnitTest.scala b/src/main/scala/unittest/UnitTest.scala
index a5d496ba..e8d82373 100644
--- a/src/main/scala/unittest/UnitTest.scala
+++ b/src/main/scala/unittest/UnitTest.scala
@@ -18,6 +18,7 @@ abstract class UnitTest extends Module with HasUnitTestIO {
 }
 
 case object UnitTests extends Field[Parameters => Seq[UnitTest]]
+case object UnitTestTimeout extends Field[Int]
 
 class UnitTestSuite(implicit p: Parameters) extends Module {
   val io = new Bundle {
@@ -39,7 +40,7 @@ class UnitTestSuite(implicit p: Parameters) extends Module {
     state := Mux(test_idx === UInt(tests.size - 1), s_done, s_start)
   }
 
-  val timer = Module(new Timer(500000, tests.size))
+  val timer = Module(new Timer(p(UnitTestTimeout), tests.size))
   timer.io.start.valid := Bool(false)
   timer.io.stop.valid := Bool(false)