riscv/rocket-chip
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Increase BTB size; fix Rocket FPU bug

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This commit is contained in:
Andrew Waterman 2014-01-17 03:53:08 -08:00
parent dfc13236d1
commit 6f028b2d52
2 changed files with 2 additions and 2 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 2249bbfbdebdd6f2a02c34793024332a08c9167d Subproject commit 029a205b207f3350e68e85d9fa69fa0e79140ac6

2
src/main/scala/RocketChip.scala
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@ -251,7 +251,7 @@ class Top extends Module {
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16) val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38)
val dc = DCacheConfig(128, 4, ntlb = 8, val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc, val rc = RocketConfiguration(tl, ic, dc,