diff --git a/rocket b/rocket
index 2249bbfb..029a205b 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 2249bbfbdebdd6f2a02c34793024332a08c9167d
+Subproject commit 029a205b207f3350e68e85d9fa69fa0e79140ac6
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 90cccf9c..deb400f7 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -251,7 +251,7 @@ class Top extends Module {
   implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
   implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
 
-  val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
+  val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38)
   val dc = DCacheConfig(128, 4, ntlb = 8, 
                         nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
   val rc = RocketConfiguration(tl, ic, dc,