riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Increase BTB size; fix Rocket FPU bug

Browse Source
This commit is contained in:
Andrew Waterman
2014-01-17 03:53:08 -08:00
parent dfc13236d1
commit 6f028b2d52
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/RocketChip.scala
View File

@ -251,7 +251,7 @@ class Top extends Module {
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38)
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc,