riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix Mux1H for bundles

Browse Source
This commit is contained in:
Andrew Waterman 2012-03-06 23:37:51 -08:00
parent 81dcb194d3
commit 6e2610b0ad
1 changed files with 12 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
rocket/src/main/scala/util.scala
View File

@ -158,16 +158,19 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
val out = gen.asOutput val out = gen.asOutput
} }
if (n > 2) { def buildMux(sel: Bits, in: Vec[T], i: Int, n: Int): T = {
var out = io.in(0).toBits & Fill(gen.getWidth, io.sel(0)) if (n == 1)
for (i <- 1 to n-1) in(i)
out = out | (io.in(i).toBits & Fill(gen.getWidth, io.sel(i))) else
io.out := out {
} else if (n == 2) { val half_n = (1 << log2up(n))/2
io.out := Mux(io.sel(1), io.in(1), io.in(0)) val left = buildMux(sel, in, i, half_n)
} else { val right = buildMux(sel, in, i + half_n, n - half_n)
io.out := io.in(0) Mux(sel(i+n-1,i+half_n).orR, right, left)
}
} }
io.out := buildMux(io.sel.toBits, io.in, 0, n)
} }