From 6e2610b0ada4c54512d0aa709ae8c644be212c00 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 6 Mar 2012 23:37:51 -0800 Subject: [PATCH] fix Mux1H for bundles --- rocket/src/main/scala/util.scala | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 7d0db909..df99e432 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -158,16 +158,19 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component val out = gen.asOutput } - if (n > 2) { - var out = io.in(0).toBits & Fill(gen.getWidth, io.sel(0)) - for (i <- 1 to n-1) - out = out | (io.in(i).toBits & Fill(gen.getWidth, io.sel(i))) - io.out := out - } else if (n == 2) { - io.out := Mux(io.sel(1), io.in(1), io.in(0)) - } else { - io.out := io.in(0) + def buildMux(sel: Bits, in: Vec[T], i: Int, n: Int): T = { + if (n == 1) + in(i) + else + { + val half_n = (1 << log2up(n))/2 + val left = buildMux(sel, in, i, half_n) + val right = buildMux(sel, in, i + half_n, n - half_n) + Mux(sel(i+n-1,i+half_n).orR, right, left) + } } + + io.out := buildMux(io.sel.toBits, io.in, 0, n) }