riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Specify some uninferrable widths

Browse Source 
It's really scary that Chisel2 passed this stuff.
This commit is contained in:
Andrew Waterman
2015-07-31 14:23:52 -07:00
parent 45cf64dbd7
commit 6d7cc37e87
3 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/btb.scala
View File

@@ -177,7 +177,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
val useUpdatePageHit = updatePageHit.orR val useUpdatePageHit = updatePageHit.orR
val doIdxPageRepl = !useUpdatePageHit val doIdxPageRepl = !useUpdatePageHit
val idxPageRepl = Wire(UInt()) val idxPageRepl = Wire(UInt(width = nPages))
val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl) val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
val idxPageUpdate = OHToUInt(idxPageUpdateOH) val idxPageUpdate = OHToUInt(idxPageUpdateOH)
val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0)) val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))

2
rocket/src/main/scala/icache.scala
View File

@@ -218,7 +218,7 @@ class ICache extends FrontendModule
val s1_tag_match = Wire(Vec(Bool(), nWays)) val s1_tag_match = Wire(Vec(Bool(), nWays))
val s2_tag_hit = Wire(Vec(Bool(), nWays)) val s2_tag_hit = Wire(Vec(Bool(), nWays))
val s2_dout = Reg(Vec(Bits(), nWays)) val s2_dout = Reg(Vec(Bits(width = code.width(rowBits)), nWays))
for (i <- 0 until nWays) { for (i <- 0 until nWays) {
val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool

2
rocket/src/main/scala/nbdcache.scala
View File

@@ -304,7 +304,7 @@ class MSHRFile extends L1HellaCacheModule {
when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data } when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
val idxMatch = Wire(Vec(Bool(), nMSHRs)) val idxMatch = Wire(Vec(Bool(), nMSHRs))
val tagList = Wire(Vec(Bits(), nMSHRs)) val tagList = Wire(Vec(Bits(width = tagBits), nMSHRs))
val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
val wbTagList = Wire(Vec(Bits(), nMSHRs)) val wbTagList = Wire(Vec(Bits(), nMSHRs))