riscv/rocket-chip
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Specify some uninferrable widths

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It's really scary that Chisel2 passed this stuff.
This commit is contained in:
Andrew Waterman
2015-07-31 14:23:52 -07:00
parent 45cf64dbd7
commit 6d7cc37e87
3 changed files with 3 additions and 3 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -304,7 +304,7 @@ class MSHRFile extends L1HellaCacheModule {
when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
val idxMatch = Wire(Vec(Bool(), nMSHRs))
val tagList = Wire(Vec(Bits(), nMSHRs))
val tagList = Wire(Vec(Bits(width = tagBits), nMSHRs))
val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
val wbTagList = Wire(Vec(Bits(), nMSHRs))