riscv/rocket-chip
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Specify some uninferrable widths

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It's really scary that Chisel2 passed this stuff.
This commit is contained in:
Andrew Waterman
2015-07-31 14:23:52 -07:00
parent 45cf64dbd7
commit 6d7cc37e87
3 changed files with 3 additions and 3 deletions
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rocket/src/main/scala/btb.scala
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@ -177,7 +177,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
val useUpdatePageHit = updatePageHit.orR
val doIdxPageRepl = !useUpdatePageHit
val idxPageRepl = Wire(UInt())
val idxPageRepl = Wire(UInt(width = nPages))
val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
val idxPageUpdate = OHToUInt(idxPageUpdateOH)
val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))