riscv/rocket-chip
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Mask interrupts during single-step

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This commit is contained in:
Andrew Waterman 2016-06-22 17:17:52 -07:00
parent 5644a2703a
commit 6d43c0a945
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/csr.scala
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@ -223,7 +223,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val all_interrupts = m_interrupts | s_interrupts
val interruptMSB = BigInt(1) << (xLen-1)
val interruptCause = interruptMSB + PriorityEncoder(all_interrupts)
io.interrupt := all_interrupts.orR || reg_singleStepped
io.interrupt := all_interrupts.orR && !io.singleStep || reg_singleStepped
io.interrupt_cause := interruptCause
io.bp := reg_bp take p(NBreakpoints)