From 6d43c0a945e284f2b885639e7cdb5e680eb0cb29 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 22 Jun 2016 17:17:52 -0700 Subject: [PATCH] Mask interrupts during single-step --- rocket/src/main/scala/csr.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index d1cc678a..d223b6b5 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -223,7 +223,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) val all_interrupts = m_interrupts | s_interrupts val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB + PriorityEncoder(all_interrupts) - io.interrupt := all_interrupts.orR || reg_singleStepped + io.interrupt := all_interrupts.orR && !io.singleStep || reg_singleStepped io.interrupt_cause := interruptCause io.bp := reg_bp take p(NBreakpoints)