riscv/rocket-chip
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nTiles -> nClients in LogicalNetworkConfig

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This commit is contained in:
Henry Cook 2013-02-28 21:03:37 -08:00
parent ea9d0b771e
commit 6d2541aced
5 changed files with 14 additions and 14 deletions
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2
rocket/src/main/scala/core.scala
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@ -8,7 +8,7 @@ import Util._
class RocketIO(implicit conf: RocketConfiguration) extends Bundle class RocketIO(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new HTIFIO(conf.lnConf.nTiles) val host = new HTIFIO(conf.lnConf.nClients)
val imem = new CPUFrontendIO()(conf.icache) val imem = new CPUFrontendIO()(conf.icache)
val vimem = new CPUFrontendIO()(conf.icache) val vimem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache) val dmem = new HellaCacheIO()(conf.dcache)

2
rocket/src/main/scala/dpath.scala
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@ -10,7 +10,7 @@ import hwacha._
class Datapath(implicit conf: RocketConfiguration) extends Component class Datapath(implicit conf: RocketConfiguration) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val host = new HTIFIO(conf.lnConf.nTiles) val host = new HTIFIO(conf.lnConf.nClients)
val ctrl = (new CtrlDpathIO).flip val ctrl = (new CtrlDpathIO).flip
val dmem = new HellaCacheIO()(conf.dcache) val dmem = new HellaCacheIO()(conf.dcache)
val ptw = (new DatapathPTWIO).flip val ptw = (new DatapathPTWIO).flip

2
rocket/src/main/scala/dpath_util.scala
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@ -104,7 +104,7 @@ object PCR
class PCR(implicit conf: RocketConfiguration) extends Component class PCR(implicit conf: RocketConfiguration) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val host = new HTIFIO(conf.lnConf.nTiles) val host = new HTIFIO(conf.lnConf.nClients)
val r = new ioReadPort(conf.nxpr, conf.xprlen) val r = new ioReadPort(conf.nxpr, conf.xprlen)
val w = new ioWritePort(conf.nxpr, conf.xprlen) val w = new ioWritePort(conf.nxpr, conf.xprlen)

20
rocket/src/main/scala/htif.scala
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@ -41,7 +41,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
implicit val lnConf = conf.ln implicit val lnConf = conf.ln
val io = new Bundle { val io = new Bundle {
val host = new HostIO(w) val host = new HostIO(w)
val cpu = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles).flip } val cpu = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients).flip }
val mem = new TileLinkIO()(conf.ln) val mem = new TileLinkIO()(conf.ln)
} }
@ -82,7 +82,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() } val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0) val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
val pcr_coreid = if (conf.ln.nTiles == 1) UFix(0) else addr(20+log2Up(conf.ln.nTiles),20) val pcr_coreid = if (conf.ln.nClients == 1) UFix(0) else addr(20+log2Up(conf.ln.nClients),20)
val pcr_wdata = packet_ram(0) val pcr_wdata = packet_ram(0)
val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
@ -182,19 +182,19 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
io.mem.release.valid := Bool(false) io.mem.release.valid := Bool(false)
io.mem.release_data.valid := Bool(false) io.mem.release_data.valid := Bool(false)
io.mem.acquire.bits.header.src := UFix(conf.ln.nTiles) io.mem.acquire.bits.header.src := UFix(conf.ln.nClients)
io.mem.acquire.bits.header.dst := UFix(0) io.mem.acquire.bits.header.dst := UFix(0)
io.mem.acquire_data.bits.header.src := UFix(conf.ln.nTiles) io.mem.acquire_data.bits.header.src := UFix(conf.ln.nClients)
io.mem.acquire_data.bits.header.dst := UFix(0) io.mem.acquire_data.bits.header.dst := UFix(0)
io.mem.release.bits.header.src := UFix(conf.ln.nTiles) io.mem.release.bits.header.src := UFix(conf.ln.nClients)
io.mem.release.bits.header.dst := UFix(0) io.mem.release.bits.header.dst := UFix(0)
io.mem.release_data.bits.header.src := UFix(conf.ln.nTiles) io.mem.release_data.bits.header.src := UFix(conf.ln.nClients)
io.mem.release_data.bits.header.dst := UFix(0) io.mem.release_data.bits.header.dst := UFix(0)
io.mem.grant_ack.bits.header.src := UFix(conf.ln.nTiles) io.mem.grant_ack.bits.header.src := UFix(conf.ln.nClients)
io.mem.grant_ack.bits.header.dst := UFix(0) io.mem.grant_ack.bits.header.dst := UFix(0)
val pcrReadData = Vec(conf.ln.nTiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } } val pcrReadData = Vec(conf.ln.nClients) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
for (i <- 0 until conf.ln.nTiles) { for (i <- 0 until conf.ln.nClients) {
val my_reset = Reg(resetVal = Bool(true)) val my_reset = Reg(resetVal = Bool(true))
val my_ipi = Reg(resetVal = Bool(false)) val my_ipi = Reg(resetVal = Bool(false))
@ -211,7 +211,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
} }
cpu.ipi_rep.valid := my_ipi cpu.ipi_rep.valid := my_ipi
cpu.ipi_req.ready := Bool(true) cpu.ipi_req.ready := Bool(true)
for (j <- 0 until conf.ln.nTiles) { for (j <- 0 until conf.ln.nClients) {
when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) { when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
my_ipi := Bool(true) my_ipi := Bool(true)
} }

2
rocket/src/main/scala/tile.scala
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@ -31,7 +31,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
val io = new Bundle { val io = new Bundle {
val tilelink = new TileLinkIO val tilelink = new TileLinkIO
val host = new HTIFIO(lnConf.nTiles) val host = new HTIFIO(lnConf.nClients)
} }
val core = new Core val core = new Core