riscv/rocket-chip
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nTiles -> nClients in LogicalNetworkConfig

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Henry Cook
2013-02-28 21:03:37 -08:00
parent ea9d0b771e
commit 6d2541aced
5 changed files with 14 additions and 14 deletions
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2
rocket/src/main/scala/core.scala
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@ -8,7 +8,7 @@ import Util._
class RocketIO(implicit conf: RocketConfiguration) extends Bundle
{
val host = new HTIFIO(conf.lnConf.nTiles)
val host = new HTIFIO(conf.lnConf.nClients)
val imem = new CPUFrontendIO()(conf.icache)
val vimem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache)