riscv/rocket-chip
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Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port

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This commit is contained in:
Andrew Waterman 2016-05-02 15:21:55 -07:00
parent c4d2d29e80
commit 6d1e82bddf
6 changed files with 14 additions and 8 deletions
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2
riscv-tools

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Subproject commit b8fe37d17fe4c5be14af6f4975056cdce81691d7 Subproject commit 5fd945be6d791a189503cd3a91c22b191a32739c

2
rocket

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Subproject commit 2b5831d9226258f15d28d16135da464f30aac603 Subproject commit 6f201e73af1c36524367ae74aa1407d1c6863675

12
src/main/scala/RocketChip.scala
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@ -11,8 +11,6 @@ import rocket.Util._
/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */ /** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
/** Number of tiles */
case object NTiles extends Field[Int]
/** Number of memory channels */ /** Number of memory channels */
case object NMemoryChannels extends Field[Int] case object NMemoryChannels extends Field[Int]
/** Number of banks per memory channel */ /** Number of banks per memory channel */
@ -130,11 +128,19 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
// Connect each tile to the HTIF // Connect each tile to the HTIF
uncore.io.htif.zip(tileList).zipWithIndex.foreach { uncore.io.htif.zip(tileList).zipWithIndex.foreach {
case ((hl, tile), i) => case ((hl, tile), i) =>
tile.io.host.timerIRQ := uncore.io.timerIRQs(i) // TODO remove
tile.io.host.id := UInt(i) tile.io.host.id := UInt(i)
tile.io.host.reset := Reg(next=Reg(next=hl.reset)) tile.io.host.reset := Reg(next=Reg(next=hl.reset))
tile.io.host.csr.req <> Queue(hl.csr.req) tile.io.host.csr.req <> Queue(hl.csr.req)
hl.csr.resp <> Queue(tile.io.host.csr.resp) hl.csr.resp <> Queue(tile.io.host.csr.resp)
// TODO move this into PRCI
tile.io.prci.interrupts.mtip := uncore.io.timerIRQs(i)
tile.io.prci.interrupts.msip := Bool(false)
tile.io.prci.interrupts.meip := Bool(false)
tile.io.prci.interrupts.seip := Bool(false)
tile.io.prci.id := UInt(i)
tile.io.prci.reset := Reg(next=Reg(next=hl.reset))
} }
// Connect the uncore to the tile memory ports, HostIO and MemIO // Connect the uncore to the tile memory ports, HostIO and MemIO

2
src/main/scala/Testing.scala
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@ -140,7 +140,7 @@ object DefaultTestSuites {
val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi") val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_) val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_)
val rv32miNames = LinkedHashSet("csr", "mcsr", "wfi", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall") val rv32miNames = LinkedHashSet("csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_) val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
val rv32u = List(rv32ui, rv32um, rv32ua) val rv32u = List(rv32ui, rv32um, rv32ua)

2
uncore

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Subproject commit 0b3199d3ae19aafe05d723d63c1991d57330f1ab Subproject commit 3e456c87d264c69a568d15ca218eb93836e8ca5d

2
zscale

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Subproject commit de370f6baa03ba47f9a39b31a36336e805047955 Subproject commit d430f0ae5bb5c32cc9d7f8c1743948667ac47246