diff --git a/riscv-tools b/riscv-tools
index b8fe37d1..5fd945be 160000
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit b8fe37d17fe4c5be14af6f4975056cdce81691d7
+Subproject commit 5fd945be6d791a189503cd3a91c22b191a32739c
diff --git a/rocket b/rocket
index 2b5831d9..6f201e73 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 2b5831d9226258f15d28d16135da464f30aac603
+Subproject commit 6f201e73af1c36524367ae74aa1407d1c6863675
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index b4b714b8..3873a745 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -11,8 +11,6 @@ import rocket.Util._
 
 /** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
 
-/** Number of tiles */
-case object NTiles extends Field[Int]
 /** Number of memory channels */
 case object NMemoryChannels extends Field[Int]
 /** Number of banks per memory channel */
@@ -130,11 +128,19 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
   // Connect each tile to the HTIF
   uncore.io.htif.zip(tileList).zipWithIndex.foreach {
     case ((hl, tile), i) =>
-      tile.io.host.timerIRQ := uncore.io.timerIRQs(i)
+      // TODO remove
       tile.io.host.id := UInt(i)
       tile.io.host.reset := Reg(next=Reg(next=hl.reset))
       tile.io.host.csr.req <> Queue(hl.csr.req)
       hl.csr.resp <> Queue(tile.io.host.csr.resp)
+
+      // TODO move this into PRCI
+      tile.io.prci.interrupts.mtip := uncore.io.timerIRQs(i)
+      tile.io.prci.interrupts.msip := Bool(false)
+      tile.io.prci.interrupts.meip := Bool(false)
+      tile.io.prci.interrupts.seip := Bool(false)
+      tile.io.prci.id := UInt(i)
+      tile.io.prci.reset := Reg(next=Reg(next=hl.reset))
   }
 
   // Connect the uncore to the tile memory ports, HostIO and MemIO
diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala
index b22a1786..b7064b5e 100644
--- a/src/main/scala/Testing.scala
+++ b/src/main/scala/Testing.scala
@@ -140,7 +140,7 @@ object DefaultTestSuites {
   val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
   val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_)
 
-  val rv32miNames = LinkedHashSet("csr", "mcsr", "wfi", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
+  val rv32miNames = LinkedHashSet("csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
   val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
 
   val rv32u = List(rv32ui, rv32um, rv32ua)
diff --git a/uncore b/uncore
index 0b3199d3..3e456c87 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 0b3199d3ae19aafe05d723d63c1991d57330f1ab
+Subproject commit 3e456c87d264c69a568d15ca218eb93836e8ca5d
diff --git a/zscale b/zscale
index de370f6b..d430f0ae 160000
--- a/zscale
+++ b/zscale
@@ -1 +1 @@
-Subproject commit de370f6baa03ba47f9a39b31a36336e805047955
+Subproject commit d430f0ae5bb5c32cc9d7f8c1743948667ac47246