From 6d10115b195334d46294a4dc55603be345813b91 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 15 Nov 2012 16:45:51 -0800 Subject: [PATCH] fix D$ tag width --- rocket/src/main/scala/nbdcache.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 5094f186..5c9bed76 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -18,12 +18,15 @@ case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy, def pgidxbits = PGIDX_BITS def offbits = OFFSET_BITS def paddrbits = ppnbits + pgidxbits - def lineaddrbits = ppnbits - offbits + def lineaddrbits = paddrbits - offbits def idxbits = log2Up(sets) def waybits = log2Up(ways) + def untagbits = offbits + idxbits def tagbits = lineaddrbits - idxbits + def ramoffbits = log2Up(MEM_DATA_BITS/8) def databytes = 8 // assumed by StoreGen/LoadGen/AMOALU def databits = databytes*8 + def wordoffbits = log2Up(databytes) } abstract class ReplacementPolicy