From 1e3ac0afa99539ba74310b1a03d0d482214a5ed2 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 13:10:30 -0700 Subject: [PATCH 1/8] back to NTILES=1 --- src/main/scala/RocketChip.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index bd35cdda..f98086c9 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -9,7 +9,7 @@ import scala.collection.mutable.ArrayBuffer import scala.collection.mutable.HashMap object DummyTopLevelConstants { - val NTILES = 2 + val NTILES = 1 val NBANKS = 1 val HTIF_WIDTH = 16 val ENABLE_SHARING = true From 0884bc97896ad40124f5cf7bc7d332997b184d60 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 13:20:38 -0700 Subject: [PATCH 2/8] fix DRAMSideLLCNull entries --- src/main/scala/RocketChip.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index f98086c9..4bf553a5 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -16,10 +16,12 @@ object DummyTopLevelConstants { val ENABLE_CLEAN_EXCLUSIVE = true val HAS_VEC = true val NL2_REL_XACTS = 1 - val NL2_ACQ_XACTS = 8 + val NL2_ACQ_XACTS = 7 val NMSHRS = 2 } +import DummyTopLevelConstants._ + object ReferenceChipBackend { val initMap = new HashMap[Component, Bool]() } @@ -91,7 +93,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge val llc_tag_leaf = Mem(512, seqRead = true) { Bits(width = 152) } val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) } //val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf) - val llc = new DRAMSideLLCNull(8, REFILL_CYCLES) + val llc = new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES) val mem_serdes = new MemSerdes(htif_width) require(clientEndpoints.length == ln.nClients) @@ -222,8 +224,6 @@ class VLSITopIO(htifWidth: Int) extends TopIO(htifWidth) { val out_mem_valid = Bool(OUTPUT) } -import DummyTopLevelConstants._ - class MemDessert extends Component { val io = new MemDesserIO(HTIF_WIDTH) val x = new MemDesser(HTIF_WIDTH) From 694ebd65cf612aef38f4c8c86ea7782c2b7bc1fe Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 15:24:25 -0700 Subject: [PATCH 3/8] push uncore --- uncore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore b/uncore index 0f675e35..3fd610b7 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 0f675e35e7503419482b12fb265ef2709a91403a +Subproject commit 3fd610b77328c0a20d94e37a58a93ddc6d7ee4de From 76cd90fc01f274e6df1e7af3d8630653ec533c11 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 15:47:42 -0700 Subject: [PATCH 4/8] parameterize number of SCRs --- src/main/scala/RocketChip.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 4bf553a5..aa3d290d 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -138,7 +138,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge io.mem_backup <> mem_serdes.io.narrow } -case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int) +case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int) class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component { @@ -153,7 +153,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf val mem_backup = new ioMemSerialized(htif_width) val mem_backup_en = Bool(INPUT) } - val htif = new RocketHTIF(htif_width) + val htif = new RocketHTIF(htif_width, conf.nSCR) val outmemsys = new OuterMemorySystem(htif_width, tileList :+ htif) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif @@ -243,7 +243,7 @@ class Top extends Component { implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1) implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS) implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) - implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5) + implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16) val dc = DCacheConfig(128, 4, ntlb = 8, From ba9bbc27dfa4792b703b919bfb684499c382587e Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 15:50:03 -0700 Subject: [PATCH 5/8] apply same change to fpga top-level --- src/main/scala/fpga.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 7a471fc5..5f46f3ef 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -46,7 +46,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit val htif = Vec(conf.nTiles) { new HTIFIO(conf.nTiles) }.flip val incoherent = Vec(conf.nTiles) { Bool() }.asInput } - val htif = new RocketHTIF(htif_width) + val htif = new RocketHTIF(htif_width, conf.nSCR) val outmemsys = new FPGAOuterMemorySystem(htif_width, tileList :+ htif) htif.io.cpu <> io.htif outmemsys.io.mem <> io.mem @@ -88,7 +88,7 @@ class FPGATop extends Component { implicit val ln = LogicalNetworkConfiguration(ntiles+nbanks+1, log2Up(ntiles)+1, nbanks, ntiles+1) implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), MEM_DATA_BITS) implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) - implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5) + implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5, nSCR = 64) val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4) val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates) From d0674af13f4fcc578072cc2d720ceba613179b5a Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 22:15:38 -0700 Subject: [PATCH 6/8] forgot to push riscv-rocket --- riscv-rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-rocket b/riscv-rocket index ee815dd3..e10bc912 160000 --- a/riscv-rocket +++ b/riscv-rocket @@ -1 +1 @@ -Subproject commit ee815dd3983f3b1a67fd3d810a513e23bdef97e4 +Subproject commit e10bc912bfaa05eba803607052b7c5c1f479c83e From 9003bc261442c0384d96ab009cc37af39fd3d259 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 22:42:57 -0700 Subject: [PATCH 7/8] push rocket --- riscv-rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-rocket b/riscv-rocket index e10bc912..f2191158 160000 --- a/riscv-rocket +++ b/riscv-rocket @@ -1 +1 @@ -Subproject commit e10bc912bfaa05eba803607052b7c5c1f479c83e +Subproject commit f2191158ac2f48cf23fbf411bf597afef23a9355 From 2c47b4388afd50ba376a8d99a890080d11e2f990 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 26 Aug 2013 14:54:49 -0700 Subject: [PATCH 8/8] push rocket --- riscv-rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-rocket b/riscv-rocket index f2191158..8e6ffeae 160000 --- a/riscv-rocket +++ b/riscv-rocket @@ -1 +1 @@ -Subproject commit f2191158ac2f48cf23fbf411bf597afef23a9355 +Subproject commit 8e6ffeae8e1877af545bce9b9fe6c23b2958e452