add verilog target to build without simulator

fsim/Makefile

@@ -15,11 +15,11 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen
 sim_dir = .
 output_dir = $(sim_dir)/output
 
-include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag
+include $(base_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim
 
 all: $(simv)
 
 clean:
-	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir
+	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*