diff --git a/Makefrag b/Makefrag
index 14951cee..fd758617 100644
--- a/Makefrag
+++ b/Makefrag
@@ -40,6 +40,10 @@ $(generated_dir)/$(FPGAMODEL)Mem.v: $(generated_dir)/$(FPGAMODEL).conf $(mem_gen
 $(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
 	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert"
 
+# Generic Verilog
+.PHONY: verilog
+verilog: $(sim_vsrcs)
+
 #--------------------------------------------------------------------
 # DRAMSim2
 #--------------------------------------------------------------------
diff --git a/fsim/Makefile b/fsim/Makefile
index f4297646..53a3a8d3 100644
--- a/fsim/Makefile
+++ b/fsim/Makefile
@@ -15,11 +15,11 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen
 sim_dir = .
 output_dir = $(sim_dir)/output
 
-include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag
+include $(base_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim
 
 all: $(simv)
 
 clean:
-	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir
+	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*
diff --git a/vsim/Makefile b/vsim/Makefile
index abc3ac82..e427e5d4 100644
--- a/vsim/Makefile
+++ b/vsim/Makefile
@@ -15,11 +15,11 @@ vlsi_mem_gen = $(base_dir)/vsim/vlsi_mem_gen
 sim_dir = .
 output_dir = $(sim_dir)/output
 
-include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag
+include $(base_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim
 
 all: $(simv)
 
 clean:
-	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir
+	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*