From 6c3269a1d863c0f049f774b75e9e45ffffeae1b5 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 17 Sep 2016 00:19:37 -0700 Subject: [PATCH] SRAM: optionally (default: true) executable --- src/main/scala/uncore/tilelink2/SRAM.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala index 2970eb78..84a775f2 100644 --- a/src/main/scala/uncore/tilelink2/SRAM.scala +++ b/src/main/scala/uncore/tilelink2/SRAM.scala @@ -4,12 +4,12 @@ package uncore.tilelink2 import Chisel._ -class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule +class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule { val node = TLManagerNode(beatBytes, TLManagerParameters( address = List(address), regionType = RegionType.UNCACHED, - executable = true, + executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes),