riscv/rocket-chip
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Purge UInt := SInt assignments

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This commit is contained in:
Andrew Waterman
2015-07-31 15:42:10 -07:00
parent 6d7cc37e87
commit 6c0e1e33ab
6 changed files with 14 additions and 14 deletions
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2
rocket/src/main/scala/tlb.scala
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@ -178,7 +178,7 @@ class TLB extends TLBModule {
// clear invalid entries on access, or all entries on a TLB flush
tag_cam.io.clear := io.ptw.invalidate || io.req.fire()
tag_cam.io.clear_mask := ~valid_array.toBits | (tag_cam.io.hits & ~tag_hits)
when (io.ptw.invalidate) { tag_cam.io.clear_mask := SInt(-1) }
when (io.ptw.invalidate) { tag_cam.io.clear_mask := ~UInt(0, entries) }
io.ptw.req.valid := state === s_request
io.ptw.req.bits.addr := r_refill_tag