riscv/rocket-chip
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Purge UInt := SInt assignments

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This commit is contained in:
Andrew Waterman
2015-07-31 15:42:10 -07:00
parent 6d7cc37e87
commit 6c0e1e33ab
6 changed files with 14 additions and 14 deletions
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2
rocket/src/main/scala/rocket.scala
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@ -198,7 +198,7 @@ class Rocket extends CoreModule
alu.io.dw := ex_ctrl.alu_dw
alu.io.fn := ex_ctrl.alu_fn
alu.io.in2 := ex_op2.toUInt
alu.io.in1 := ex_op1
alu.io.in1 := ex_op1.toUInt
// multiplier and divider
val div = Module(new MulDiv(mulUnroll = if(params(FastMulDiv)) 8 else 1,