riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

push accel/rocket dmem port back to rocket

Browse Source
This commit is contained in:
Yunsup Lee
2014-01-16 16:01:41 -08:00
parent ebec444ad2
commit 6bbbf36979
1 changed files with 3 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/tile.scala
View File

@@ -60,8 +60,10 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
if (!conf.rocc.isEmpty) {
val rocc = Module((conf.rocc.get)(conf))
val dcIF = Module(new SimpleHellaCacheIF)
dcIF.io.requestor <> rocc.io.mem
core.io.rocc <> rocc.io
dcacheArb.io.requestor(2) <> rocc.io.mem
dcacheArb.io.requestor(2) <> dcIF.io.cache
memArb.io.in(roccPortId) <> rocc.io.imem
ptw.io.requestor(2) <> rocc.io.iptw
ptw.io.requestor(3) <> rocc.io.dptw