From 6bbbf369790794aa1c8d2e2796ba64d4e6d745f9 Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Thu, 16 Jan 2014 16:01:41 -0800
Subject: [PATCH] push accel/rocket dmem port back to rocket

---
 rocket/src/main/scala/tile.scala | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 6423c40f..618a30bc 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -60,8 +60,10 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
 
   if (!conf.rocc.isEmpty) {
     val rocc = Module((conf.rocc.get)(conf))
+    val dcIF = Module(new SimpleHellaCacheIF)
+    dcIF.io.requestor <> rocc.io.mem
     core.io.rocc <> rocc.io
-    dcacheArb.io.requestor(2) <> rocc.io.mem
+    dcacheArb.io.requestor(2) <> dcIF.io.cache
     memArb.io.in(roccPortId) <> rocc.io.imem
     ptw.io.requestor(2) <> rocc.io.iptw
     ptw.io.requestor(3) <> rocc.io.dptw