diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index f7f41a94..8a20f137 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -433,13 +433,13 @@ class Control(implicit conf: RocketConfiguration) extends Module
 
   val (id_xcpt, id_cause) = checkExceptions(List(
     (id_interrupt,                                    id_interrupt_cause),
-    (io.imem.resp.bits.xcpt_ma,                       UInt(0)),
-    (io.imem.resp.bits.xcpt_if,                       UInt(1)),
-    (!id_int_val || id_csr_invalid,                   UInt(2)),
-    (id_privileged && !io.dpath.status.s,             UInt(3)),
-    ((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(4)),
-    (id_syscall,                                      UInt(6)),
-    (id_rocc_val && !io.dpath.status.er,              UInt(12))))
+    (io.imem.resp.bits.xcpt_ma,                       UInt(Causes.misaligned_fetch)),
+    (io.imem.resp.bits.xcpt_if,                       UInt(Causes.fault_fetch)),
+    (!id_int_val || id_csr_invalid,                   UInt(Causes.illegal_instruction)),
+    (id_privileged && !io.dpath.status.s,             UInt(Causes.privileged_instruction)),
+    ((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(Causes.fp_disabled)),
+    (id_syscall,                                      UInt(Causes.syscall)),
+    (id_rocc_val && !io.dpath.status.er,              UInt(Causes.accelerator_disabled))))
 
   ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid
   when (id_xcpt) { ex_reg_cause := id_cause }
@@ -496,7 +496,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
 
   val (ex_xcpt, ex_cause) = checkExceptions(List(
     (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
-    (ex_reg_fp_val && io.fpu.illegal_rm,   UInt(2))))
+    (ex_reg_fp_val && io.fpu.illegal_rm,   UInt(Causes.illegal_instruction))))
   
   mem_reg_replay := replay_ex && !take_pc_wb
   mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb && !mem_reg_replay_next
@@ -533,10 +533,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
 
   val (mem_xcpt, mem_cause) = checkExceptions(List(
     (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
-    (mem_reg_mem_val && io.dmem.xcpt.ma.ld,  UInt( 8)),
-    (mem_reg_mem_val && io.dmem.xcpt.ma.st,  UInt( 9)),
-    (mem_reg_mem_val && io.dmem.xcpt.pf.ld,  UInt(10)),
-    (mem_reg_mem_val && io.dmem.xcpt.pf.st,  UInt(11))))
+    (mem_reg_mem_val && io.dmem.xcpt.ma.ld,  UInt(Causes.misaligned_load)),
+    (mem_reg_mem_val && io.dmem.xcpt.ma.st,  UInt(Causes.misaligned_store)),
+    (mem_reg_mem_val && io.dmem.xcpt.pf.ld,  UInt(Causes.fault_load)),
+    (mem_reg_mem_val && io.dmem.xcpt.pf.st,  UInt(Causes.fault_store))))
 
   val dcache_kill_mem = mem_reg_wen && io.dmem.replay_next.valid // structural hazard on writeback port
   val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala
index 5acb84a8..2d91d92c 100644
--- a/rocket/src/main/scala/instructions.scala
+++ b/rocket/src/main/scala/instructions.scala
@@ -5,14 +5,14 @@ import Node._
 
 /* Automatically generated by parse-opcodes */
 object Instructions {
-  def JAL                = Bits("b?????????????????????????1101111")
-  def JALR               = Bits("b?????????????????000?????1100111")
   def BEQ                = Bits("b?????????????????000?????1100011")
   def BNE                = Bits("b?????????????????001?????1100011")
   def BLT                = Bits("b?????????????????100?????1100011")
   def BGE                = Bits("b?????????????????101?????1100011")
   def BLTU               = Bits("b?????????????????110?????1100011")
   def BGEU               = Bits("b?????????????????111?????1100011")
+  def JALR               = Bits("b?????????????????000?????1100111")
+  def JAL                = Bits("b?????????????????????????1101111")
   def LUI                = Bits("b?????????????????????????0110111")
   def AUIPC              = Bits("b?????????????????????????0010111")
   def ADDI               = Bits("b?????????????????000?????0010011")
@@ -185,6 +185,36 @@ object Instructions {
   def CUSTOM3_RD_RS1     = Bits("b?????????????????110?????1111011")
   def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
 }
+object Causes {
+  val misaligned_fetch = 0x0
+  val fault_fetch = 0x1
+  val illegal_instruction = 0x2
+  val privileged_instruction = 0x3
+  val fp_disabled = 0x4
+  val syscall = 0x6
+  val breakpoint = 0x7
+  val misaligned_load = 0x8
+  val misaligned_store = 0x9
+  val fault_load = 0xa
+  val fault_store = 0xb
+  val accelerator_disabled = 0xc
+  val all = {
+    val res = collection.mutable.ArrayBuffer[Int]()
+    res += misaligned_fetch
+    res += fault_fetch
+    res += illegal_instruction
+    res += privileged_instruction
+    res += fp_disabled
+    res += syscall
+    res += breakpoint
+    res += misaligned_load
+    res += misaligned_store
+    res += fault_load
+    res += fault_store
+    res += accelerator_disabled
+    res.toArray
+  }
+}
 object CSRs {
   val fflags = 0x1
   val frm = 0x2