diff --git a/chisel3 b/chisel3
index 0ad47ff9..3ae577bc 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit 0ad47ff929aa084d6aff4d378b32968ef19b97c7
+Subproject commit 3ae577bc710b3767f47403a3d055e84815a30043
diff --git a/firrtl b/firrtl
index 592ee2fb..a73efa2f 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 592ee2fbc53219a39bf2da505fd761b412bf5cff
+Subproject commit a73efa2f67428101cf0984a8fb8ac3ebf32b914b
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index d3199ccc..5cdf06b2 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -215,6 +215,7 @@ class DefaultConfig extends Config (
         true
       }
       case NExtInterrupts => 2
+      case NExtMMIOChannels => 0
       case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
       case FDivSqrt => true
       case SFMALatency => 2
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 30e66045..825b6b1a 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -19,6 +19,8 @@ case object NBanksPerMemoryChannel extends Field[Int]
 case object BankIdLSB extends Field[Int]
 /** Number of outstanding memory requests */
 case object NOutstandingMemReqsPerChannel extends Field[Int]
+/** Number of exteral MMIO ports */
+case object NExtMMIOChannels extends Field[Int]
 /** Whether to divide HTIF clock */
 case object UseHtifClockDiv extends Field[Boolean]
 /** Function for building some kind of coherence manager agent */
@@ -77,8 +79,8 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
 
 class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
   val mem = Vec(nMemChannels, new NastiIO)
-  val mmio = new NastiIO
   val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
+  val mmio = Vec(p(NExtMMIOChannels), new NastiIO)
 }
 
 object TopUtils {
@@ -142,13 +144,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
   uncore.io.interrupts <> io.interrupts
 
   io.mmio <> uncore.io.mmio
-  io.mem.zip(uncore.io.mem).foreach { case (outer, inner) =>
-    outer <> inner
-    // Memory cache type should be normal non-cacheable bufferable
-    // TODO why is this happening here?  Would 0000 (device) be OK instead?
-    outer.ar.bits.cache := UInt("b0011")
-    outer.aw.bits.cache := UInt("b0011")
-  }
+  io.mem <> uncore.io.mem
 }
 
 /** Wrapper around everything that isn't a Tile.
@@ -164,7 +160,7 @@ class Uncore(implicit val p: Parameters) extends Module
     val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
     val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
     val prci = Vec(nTiles, new PRCITileIO).asOutput
-    val mmio = new NastiIO
+    val mmio = Vec(p(NExtMMIOChannels), new NastiIO)
     val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
   }
 
@@ -241,7 +237,12 @@ class Uncore(implicit val p: Parameters) extends Module
     val debugModuleAddr = ioAddrHashMap("int:debug")
     debugModule.io <> mmioNetwork.io.out(debugModuleAddr.port)
 
-    TopUtils.connectTilelinkNasti(io.mmio, mmioNetwork.io.out(ioAddrHashMap("ext").port))
+    val mmioEndpoint = p(NExtMMIOChannels) match {
+      case 0 => Module(new NastiErrorSlave).io
+      case 1 => io.mmio(0)
+      // The memory map presently has only one external I/O region
+    }
+    TopUtils.connectTilelinkNasti(mmioEndpoint, mmioNetwork.io.out(ioAddrHashMap("ext").port))
   }
 }
 
@@ -313,6 +314,11 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     icPort <> narrow.io.out
   }
 
-  for ((nasti, tl) <- io.mem zip mem_ic.io.out)
+  for ((nasti, tl) <- io.mem zip mem_ic.io.out) {
     TopUtils.connectTilelinkNasti(nasti, tl)(outermostTLParams)
+    // Memory cache type should be normal non-cacheable bufferable
+    // TODO why is this happening here?  Would 0000 (device) be OK instead?
+    nasti.ar.bits.cache := UInt("b0011")
+    nasti.aw.bits.cache := UInt("b0011")
+  }
 }
diff --git a/src/main/scala/TestBench.scala b/src/main/scala/TestBench.scala
index 54a658e9..8d788ef1 100644
--- a/src/main/scala/TestBench.scala
+++ b/src/main/scala/TestBench.scala
@@ -180,6 +180,7 @@ object TestBenchGeneration extends FileSystemUtilities {
 
     .io_mem_${i}_w_valid (w_valid_delay_$i),
     .io_mem_${i}_w_ready (w_ready_delay_$i),
+    .io_mem_${i}_w_bits_id (),
     .io_mem_${i}_w_bits_strb (w_strb_delay_$i),
     .io_mem_${i}_w_bits_data (w_data_delay_$i),
     .io_mem_${i}_w_bits_last (w_last_delay_$i),
diff --git a/uncore b/uncore
index 36d6a151..cf7534a5 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 36d6a15155c38af0878806bd55fc5ff31811a47c
+Subproject commit cf7534a5369e8af03e8d793c6b32f36916c1a13b