Avoid spurious D$ assertion failures
For the Rocket pipeline, this fix is needless and the problem is that the assertion is too conservative, but I solved it this way to avoid problems for other plausible use cases where physical and virtual accesses are intermixed.
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@ -670,8 +670,8 @@ class HellaCache extends L1HellaCacheModule {
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io.cpu.xcpt.ma.ld := s1_read && misaligned
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io.cpu.xcpt.ma.ld := s1_read && misaligned
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io.cpu.xcpt.ma.st := s1_write && misaligned
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io.cpu.xcpt.ma.st := s1_write && misaligned
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io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld
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io.cpu.xcpt.pf.ld := !s1_req.phys && s1_read && dtlb.io.resp.xcpt_ld
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io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st
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io.cpu.xcpt.pf.st := !s1_req.phys && s1_write && dtlb.io.resp.xcpt_st
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assert (!(Reg(next=
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assert (!(Reg(next=
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(io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&
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(io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&
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