From 6a9390c50e11fbc9d1f39d5f2ed7eff3aaa6353c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 19 May 2015 02:56:20 -0700 Subject: [PATCH] Avoid spurious D$ assertion failures For the Rocket pipeline, this fix is needless and the problem is that the assertion is too conservative, but I solved it this way to avoid problems for other plausible use cases where physical and virtual accesses are intermixed. --- rocket/src/main/scala/nbdcache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index e3f7d650..95cde564 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -670,8 +670,8 @@ class HellaCache extends L1HellaCacheModule { io.cpu.xcpt.ma.ld := s1_read && misaligned io.cpu.xcpt.ma.st := s1_write && misaligned - io.cpu.xcpt.pf.ld := s1_read && dtlb.io.resp.xcpt_ld - io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st + io.cpu.xcpt.pf.ld := !s1_req.phys && s1_read && dtlb.io.resp.xcpt_ld + io.cpu.xcpt.pf.st := !s1_req.phys && s1_write && dtlb.io.resp.xcpt_st assert (!(Reg(next= (io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&