riscv/rocket-chip
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rocketchip: pull rtcTick out of the coreplex

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This commit is contained in:
Wesley W. Terpstra
2016-10-28 22:37:46 -07:00
parent 5bca13ebdb
commit 688e1bffdf
2 changed files with 5 additions and 2 deletions
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src/main/scala/rocketchip/BaseTop.scala
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@@ -69,8 +69,10 @@ trait TopNetworkModule extends HasPeripheryParameters {
val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)
val coreplexSlave: Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.slave)
val coreplexDebug: DebugBusIO = Wire(outer.coreplex.module.io.debug)
val coreplexRtc : Bool = Wire(outer.coreplex.module.io.rtcTick)
io.success := outer.coreplex.module.io.success
coreplexRtc := Counter(p(rocketchip.RTCPeriod)).inc()
}
/** Base Top with no Periphery */