From 688e1bffdf7d1b2bebd0a198cef3bdc6c6759b23 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 28 Oct 2016 22:37:46 -0700
Subject: [PATCH] rocketchip: pull rtcTick out of the coreplex

---
 src/main/scala/coreplex/BaseCoreplex.scala | 5 +++--
 src/main/scala/rocketchip/BaseTop.scala    | 2 ++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index ee00d10f..af6abaf0 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -122,9 +122,10 @@ trait CoreplexRISCVBundle {
 
   val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
   val slave = Vec(nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
+  val debug = new DebugBusIO().flip
+  val rtcTick = Bool(INPUT)
   val resetVector = UInt(INPUT, p(XLen))
   val success = Bool(OUTPUT) // used for testing
-  val debug = new DebugBusIO().flip
 }
 
 trait CoreplexRISCVModule {
@@ -215,7 +216,7 @@ trait CoreplexRISCVModule {
   }
 
   outer.debug.module.io.db <> io.debug
-  outer.clint.module.io.rtcTick := Counter(p(rocketchip.RTCPeriod)).inc()
+  outer.clint.module.io.rtcTick := io.rtcTick
 
   // Coreplex doesn't know when to stop running
   io.success := Bool(false)
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index a560ad6c..a66276bc 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -69,8 +69,10 @@ trait TopNetworkModule extends HasPeripheryParameters {
   val coreplexMem  : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)
   val coreplexSlave: Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.slave)
   val coreplexDebug: DebugBusIO                    = Wire(outer.coreplex.module.io.debug)
+  val coreplexRtc  : Bool                          = Wire(outer.coreplex.module.io.rtcTick)
 
   io.success := outer.coreplex.module.io.success
+  coreplexRtc := Counter(p(rocketchip.RTCPeriod)).inc()
 }
 
 /** Base Top with no Periphery */