riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #239 from ucb-bar/move_rtc

Browse Source 
Move RTC
This commit is contained in:
Andrew Waterman 2016-09-02 15:17:49 -07:00 committed by GitHub
commit 6872000f5e
4 changed files with 16 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/main/scala/coreplex/Configs.scala
View File

@ -129,7 +129,6 @@ class BaseCoreplexConfig extends Config (
case MtvecInit => BigInt(0x1010)
case MtvecWritable => true
//Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
log2Up(site(TLKey(site(TLId))).nClients)

8
src/main/scala/coreplex/Coreplex.scala
View File

@ -30,8 +30,6 @@ case object ConfigString extends Field[Array[Byte]]
case object NExtInterrupts extends Field[Int]
/** Interrupt controller configuration */
case object PLICKey extends Field[PLICConfig]
/** Number of clock cycles per RTC tick */
case object RTCPeriod extends Field[Int]
/** The file to read the BootROM contents from */
case object BootROMFile extends Field[String]
/** Export an external MMIO slave port */
@ -73,6 +71,7 @@ class Uncore(implicit val p: Parameters) extends Module
val mmio = exportMMIO.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val debug = new DebugBusIO()(p).flip
val rtcTick = Bool(INPUT)
}
val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0)
@ -124,7 +123,7 @@ class Uncore(implicit val p: Parameters) extends Module
val prci = Module(new PRCI)
prci.io.tl <> mmioNetwork.port("int:prci")
io.prci := prci.io.tiles
prci.io.rtcTick := Counter(p(RTCPeriod)).inc() // placeholder for real RTC
prci.io.rtcTick := io.rtcTick
for (i <- 0 until nTiles) {
prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
@ -237,6 +236,7 @@ abstract class Coreplex(implicit val p: Parameters) extends Module
val mmio = p(ExportMMIOPort).option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val debug = new DebugBusIO()(p).flip
val rtcTick = new Bool(INPUT)
val extra = p(ExtraCoreplexPorts)(p)
val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
}
@ -269,6 +269,8 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
tile.io.prci <> prci
}
uncore.io.rtcTick := io.rtcTick
// Connect the uncore to the tile memory ports, HostIO and MemIO
uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten

2
src/main/scala/rocketchip/Configs.scala
View File

@ -153,6 +153,8 @@ class BasePlatformConfig extends Config (
case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case RTCTick => (p: Parameters, t_io: Bundle, p_io:Bundle) => Counter(p(RTCPeriod)).inc()
case _ => throw new CDEMatchError
}})

9
src/main/scala/rocketchip/RocketChip.scala
View File

@ -53,6 +53,10 @@ case object ExtMemSize extends Field[Long]
**/
case object NExtTopInterrupts extends Field[Int]
case object NExtPeripheryInterrupts extends Field[Int]
/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
case object RTCTick extends Field[(Parameters, Bundle, Bundle) => Bool]
case object RTCPeriod extends Field[Int]
/** Utility trait for quick access to some relevant parameters */
trait HasTopLevelParameters {
@ -194,9 +198,14 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
coreplex.io.interrupts <> (periphery.io.interrupts ++ io.interrupts)
io.extra <> periphery.io.extra
coreplex.io.rtcTick := p(RTCTick)(p, io.extra, periphery.io.extra)
p(ConnectExtraPorts)(io.extra, coreplex.io.extra, p)
}
class Periphery(implicit val p: Parameters) extends Module
with HasTopLevelParameters {
val io = new Bundle {