riscv/rocket-chip
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Merge pull request #239 from ucb-bar/move_rtc

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Move RTC
This commit is contained in:
Andrew Waterman
2016-09-02 15:17:49 -07:00
committed by GitHub
parent c05ba1e864 af364bc7bc
commit 6872000f5e
4 changed files with 16 additions and 4 deletions
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2
src/main/scala/rocketchip/Configs.scala
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@ -153,6 +153,8 @@ class BasePlatformConfig extends Config (
case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case RTCTick => (p: Parameters, t_io: Bundle, p_io:Bundle) => Counter(p(RTCPeriod)).inc()
case _ => throw new CDEMatchError
}})

9
src/main/scala/rocketchip/RocketChip.scala
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@ -53,6 +53,10 @@ case object ExtMemSize extends Field[Long]
**/
case object NExtTopInterrupts extends Field[Int]
case object NExtPeripheryInterrupts extends Field[Int]
/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
case object RTCTick extends Field[(Parameters, Bundle, Bundle) => Bool]
case object RTCPeriod extends Field[Int]
/** Utility trait for quick access to some relevant parameters */
trait HasTopLevelParameters {
@ -194,9 +198,14 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
coreplex.io.interrupts <> (periphery.io.interrupts ++ io.interrupts)
io.extra <> periphery.io.extra
coreplex.io.rtcTick := p(RTCTick)(p, io.extra, periphery.io.extra)
p(ConnectExtraPorts)(io.extra, coreplex.io.extra, p)
}
class Periphery(implicit val p: Parameters) extends Module
with HasTopLevelParameters {
val io = new Bundle {