riscv/rocket-chip
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Merge pull request #239 from ucb-bar/move_rtc

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Move RTC
This commit is contained in:
Andrew Waterman
2016-09-02 15:17:49 -07:00
committed by GitHub
parent c05ba1e864 af364bc7bc
commit 6872000f5e
4 changed files with 16 additions and 4 deletions
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1
src/main/scala/coreplex/Configs.scala
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@ -129,7 +129,6 @@ class BaseCoreplexConfig extends Config (
case MtvecInit => BigInt(0x1010)
case MtvecWritable => true
//Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
log2Up(site(TLKey(site(TLId))).nClients)

8
src/main/scala/coreplex/Coreplex.scala
View File

@ -30,8 +30,6 @@ case object ConfigString extends Field[Array[Byte]]
case object NExtInterrupts extends Field[Int]
/** Interrupt controller configuration */
case object PLICKey extends Field[PLICConfig]
/** Number of clock cycles per RTC tick */
case object RTCPeriod extends Field[Int]
/** The file to read the BootROM contents from */
case object BootROMFile extends Field[String]
/** Export an external MMIO slave port */
@ -73,6 +71,7 @@ class Uncore(implicit val p: Parameters) extends Module
val mmio = exportMMIO.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val debug = new DebugBusIO()(p).flip
val rtcTick = Bool(INPUT)
}
val outmemsys = if (nCachedTilePorts + nUncachedTilePorts > 0)
@ -124,7 +123,7 @@ class Uncore(implicit val p: Parameters) extends Module
val prci = Module(new PRCI)
prci.io.tl <> mmioNetwork.port("int:prci")
io.prci := prci.io.tiles
prci.io.rtcTick := Counter(p(RTCPeriod)).inc() // placeholder for real RTC
prci.io.rtcTick := io.rtcTick
for (i <- 0 until nTiles) {
prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
@ -237,6 +236,7 @@ abstract class Coreplex(implicit val p: Parameters) extends Module
val mmio = p(ExportMMIOPort).option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val debug = new DebugBusIO()(p).flip
val rtcTick = new Bool(INPUT)
val extra = p(ExtraCoreplexPorts)(p)
val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
}
@ -269,6 +269,8 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
tile.io.prci <> prci
}
uncore.io.rtcTick := io.rtcTick
// Connect the uncore to the tile memory ports, HostIO and MemIO
uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten