riscv/rocket-chip
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Fix PLIC instantiation when S-mode is disabled

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This commit is contained in:
Andrew Waterman
2016-05-13 11:22:46 -07:00
parent 6aa708bcee
commit 684d902059
2 changed files with 9 additions and 6 deletions
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3
src/main/scala/RocketChip.scala
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@ -222,7 +222,8 @@ class Uncore(implicit val p: Parameters) extends Module
prci.io.id := UInt(i)
prci.io.interrupts.mtip := rtc.io.irqs(i)
prci.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
prci.io.interrupts.seip := plic.io.harts(plic.cfg.context(i, 'S'))
if (p(UseVM))
prci.io.interrupts.seip := plic.io.harts(plic.cfg.context(i, 'S'))
prci.io.interrupts.debug := Bool(false)
io.prci(i) := prci.io.tile