From 684d90205905c6c68089b3d9a340dbfa6a86c3d8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 13 May 2016 11:22:46 -0700 Subject: [PATCH] Fix PLIC instantiation when S-mode is disabled --- src/main/scala/Configs.scala | 12 +++++++----- src/main/scala/RocketChip.scala | 3 ++- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 5cdf06b2..693f76b6 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -93,11 +93,13 @@ class DefaultConfig extends Config ( res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n" res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n" res append s" };\n" - res append s" s {\n" - res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n" - res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n" - res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n" - res append s" };\n" + if (site(UseVM)) { + res append s" s {\n" + res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n" + res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n" + res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n" + res append s" };\n" + } res append s" };\n" res append " };\n" res append " };\n" diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 825b6b1a..83400d80 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -222,7 +222,8 @@ class Uncore(implicit val p: Parameters) extends Module prci.io.id := UInt(i) prci.io.interrupts.mtip := rtc.io.irqs(i) prci.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M')) - prci.io.interrupts.seip := plic.io.harts(plic.cfg.context(i, 'S')) + if (p(UseVM)) + prci.io.interrupts.seip := plic.io.harts(plic.cfg.context(i, 'S')) prci.io.interrupts.debug := Bool(false) io.prci(i) := prci.io.tile