riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fix PLIC instantiation when S-mode is disabled

Browse Source
This commit is contained in:
Andrew Waterman
2016-05-13 11:22:46 -07:00
parent 6aa708bcee
commit 684d902059
2 changed files with 9 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/main/scala/Configs.scala
View File

@ -93,11 +93,13 @@ class DefaultConfig extends Config (
res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
res append s" };\n"
res append s" s {\n"
res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
res append s" };\n"
if (site(UseVM)) {
res append s" s {\n"
res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
res append s" };\n"
}
res append s" };\n"
res append " };\n"
res append " };\n"