riscv/rocket-chip
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index extraction bug

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This commit is contained in:
Henry Cook
2016-03-10 17:35:22 -08:00
parent e2185d40f6
commit 67e711844a
1 changed files with 2 additions and 2 deletions
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4
uncore/src/main/scala/cache.scala
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@@ -784,8 +784,8 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
} }
// These IOs are used for routing in the parent // These IOs are used for routing in the parent
val iacq_in_same_set = inSameSet(xact_addr_idx, io.iacq().addr_block) val iacq_in_same_set = inSameSet(xact_addr_block, io.iacq().addr_block)
val irel_in_same_set = inSameSet(xact_addr_idx,io.irel().addr_block) val irel_in_same_set = inSameSet(xact_addr_block, io.irel().addr_block)
val before_wb_alloc = Vec(s_meta_read, s_meta_resp, s_wb_req).contains(state) val before_wb_alloc = Vec(s_meta_read, s_meta_resp, s_wb_req).contains(state)
io.matches.iacq := (state =/= s_idle) && iacq_in_same_set io.matches.iacq := (state =/= s_idle) && iacq_in_same_set
io.matches.irel := (state =/= s_idle) && io.matches.irel := (state =/= s_idle) &&