riscv/rocket-chip
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Explicitly zap some S-mode CSRs when not using S-mode

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This commit is contained in:
Andrew Waterman 2016-10-04 22:23:20 -07:00
parent 968851f7e3
commit 67593fdf2d
1 changed files with 10 additions and 0 deletions
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10
src/main/scala/rocket/csr.scala
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@ -626,6 +626,16 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
reg_mip := io.interrupts
reg_dcsr.debugint := io.interrupts.debug
if (!usingVM) {
reg_mideleg := 0
reg_medeleg := 0
reg_mscounteren := 0
}
if (!usingUser) {
reg_mucounteren := 0
}
reg_sptbr.asid := 0
if (nBreakpoints <= 1) reg_tselect := 0
if (nBreakpoints >= 1)