From 67593fdf2d1a78970f2e9eb72e8fc1297ef2926b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 4 Oct 2016 22:23:20 -0700 Subject: [PATCH] Explicitly zap some S-mode CSRs when not using S-mode --- src/main/scala/rocket/csr.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/main/scala/rocket/csr.scala b/src/main/scala/rocket/csr.scala index dc11f354..1aeaca94 100644 --- a/src/main/scala/rocket/csr.scala +++ b/src/main/scala/rocket/csr.scala @@ -626,6 +626,16 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) reg_mip := io.interrupts reg_dcsr.debugint := io.interrupts.debug + if (!usingVM) { + reg_mideleg := 0 + reg_medeleg := 0 + reg_mscounteren := 0 + } + + if (!usingUser) { + reg_mucounteren := 0 + } + reg_sptbr.asid := 0 if (nBreakpoints <= 1) reg_tselect := 0 if (nBreakpoints >= 1)