From 67404a665b723642d35a076bf20555968f04ca87 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 19 Apr 2017 16:52:23 -0700 Subject: [PATCH] When not using a cache, LR/SC isn't legal even on cacheable memory --- src/main/scala/rocket/TLB.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index 7ecafb3d..51903d48 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -188,9 +188,10 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters (if (vpnBits == vpnBitsExtended) Bool(false) else vpn(vpnBits) =/= vpn(vpnBits-1)) + val lrscAllowed = Mux(Bool(usingDataScratchpad), 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) | - Mux(Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC), ~c_array, 0.U) + Mux(Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC), ~lrscAllowed, 0.U) val ae_ld_array = Mux(isRead(io.req.bits.cmd), ae_array | ~pr_array, 0.U) val ae_st_array = Mux(isWrite(io.req.bits.cmd), ae_array | ~pw_array, 0.U) |