diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala
index b77ecc10..20a02366 100644
--- a/uncore/src/main/scala/cache.scala
+++ b/uncore/src/main/scala/cache.scala
@@ -11,7 +11,6 @@ case object NWays extends Field[Int]
 case object RowBits extends Field[Int]
 case object Replacer extends Field[() => ReplacementPolicy]
 case object AmoAluOperandBits extends Field[Int]
-case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
 case object NPrimaryMisses extends Field[Int]
 case object NSecondaryMisses extends Field[Int]
 case object CacheBlockBytes extends Field[Int]
@@ -169,6 +168,8 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
   io.write.ready := !rst
 }
 
+case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
+
 trait HasL2HellaCacheParameters extends HasCacheParameters with HasCoherenceAgentParameters {
   val idxMSB = idxBits-1
   val idxLSB = 0
diff --git a/uncore/src/main/scala/rtc.scala b/uncore/src/main/scala/rtc.scala
index ed0932c0..e292cb3d 100644
--- a/uncore/src/main/scala/rtc.scala
+++ b/uncore/src/main/scala/rtc.scala
@@ -8,8 +8,7 @@ case object RTCPeriod extends Field[Int]
 class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule {
   val io = new NastiIO
 
-  private val addrMap = new AddrHashMap(p(NastiAddrMap))
-
+  val addrMap = new AddrHashMap(p(GlobalAddrMap))
   val addrTable = Vec.tabulate(nCores) { i =>
     UInt(addrMap(s"conf:csr$i").start + csr_MTIME * scrDataBytes)
   }