riscv/rocket-chip
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Merge [shm]call into ecall, [shm]ret into eret

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This commit is contained in:
Andrew Waterman
2015-03-17 02:24:41 -07:00
parent 2c875555a2
commit 66388be1ce
3 changed files with 18 additions and 29 deletions
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16
rocket/src/main/scala/csr.scala
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@@ -187,14 +187,12 @@ class CSRFile extends CoreModule
Mux(io.rw.cmd === CSR.S, io.rw.rdata | io.rw.wdata,
host_pcr_bits.data)))
val opcode = io.rw.addr(3,0)
// The following comparison is meant to be opcode === SFENCE_VM(23,20). But
// FOR SOME FUCKING REASON, extracting SFENCE_VM(23,20) gives 3, not 4.
val insn_sfence_vm = opcode === 4 && system_insn && priv_sufficient
val insn_redirect_trap = opcode === MRTS(23,20) && system_insn && priv_sufficient
val insn_ret = opcode === SRET(23,20) /* or H/MRET */ && io.rw.addr(1) && system_insn && priv_sufficient
val insn_break = opcode === SBREAK(23,20) && io.rw.addr(0) && system_insn && priv_sufficient
val insn_call = opcode === SCALL(23,20) /* or H/MCALL */ && system_insn && priv_sufficient
val opcode = io.rw.addr
val insn_call = !opcode(8) && !opcode(0) && system_insn && priv_sufficient
val insn_break = !opcode(8) && opcode(0) && system_insn && priv_sufficient
val insn_ret = opcode(8) && !opcode(0) && system_insn && priv_sufficient
val insn_sfence_vm = opcode(8) && opcode(0) && system_insn && priv_sufficient
val insn_redirect_trap = opcode(2) && system_insn && priv_sufficient
val csr_xcpt = (cpu_wen && read_only) ||
(cpu_ren && (!priv_sufficient || !addr_valid || fp_csr && !io.status.fs.orR)) ||
@@ -228,7 +226,7 @@ class CSRFile extends CoreModule
when (csr_xcpt) {
reg_mcause := Causes.illegal_instruction
when (insn_break) { reg_mcause := Causes.breakpoint }
when (insn_call) { reg_mcause := Causes.scall + csr_addr_priv }
when (insn_call) { reg_mcause := Causes.ecall }
}
reg_mbadaddr := io.pc

2
rocket/src/main/scala/ctrl.scala
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@@ -216,8 +216,6 @@ object XDecode extends DecodeConstants
SCALL-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
SBREAK-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
SRET-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
HCALL-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
MRET-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
MRTS-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N),
CSRRW-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.W,N,N,N),
CSRRS-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.S,N,N,N),

29
rocket/src/main/scala/instructions.scala
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@@ -95,12 +95,9 @@ object Instructions {
def SC_D = Bits("b00011????????????011?????0101111")
def SCALL = Bits("b00000000000000000000000001110011")
def SBREAK = Bits("b00000000000100000000000001110011")
def SRET = Bits("b00010000001000000000000001110011")
def SFENCE_VM = Bits("b000100000100?????000000001110011")
def HCALL = Bits("b00010000000000000000000001110011")
def MCALL = Bits("b00100000000000000000000001110011")
def MRET = Bits("b00110000001000000000000001110011")
def MRTS = Bits("b00110000100100000000000001110011")
def SRET = Bits("b00010000000000000000000001110011")
def SFENCE_VM = Bits("b000100000001?????000000001110011")
def MRTS = Bits("b00110000010100000000000001110011")
def CSRRW = Bits("b?????????????????001?????1110011")
def CSRRS = Bits("b?????????????????010?????1110011")
def CSRRC = Bits("b?????????????????011?????1110011")
@@ -198,27 +195,23 @@ object Causes {
val misaligned_fetch = 0x0
val fault_fetch = 0x1
val illegal_instruction = 0x2
val scall = 0x4
val hcall = 0x5
val mcall = 0x6
val breakpoint = 0x7
val misaligned_load = 0x8
val fault_load = 0x9
val misaligned_store = 0xa
val fault_store = 0xb
val misaligned_load = 0x4
val fault_load = 0x5
val misaligned_store = 0x6
val fault_store = 0x7
val ecall = 0x8
val breakpoint = 0x9
val all = {
val res = collection.mutable.ArrayBuffer[Int]()
res += misaligned_fetch
res += fault_fetch
res += illegal_instruction
res += scall
res += hcall
res += mcall
res += breakpoint
res += misaligned_load
res += fault_load
res += misaligned_store
res += fault_store
res += ecall
res += breakpoint
res.toArray
}
}