Merge remote-tracking branch 'origin/master' into rocc-fpu-port

2015-10-22 16:38:28 -07:00
parent 942f6a7d7f 0c587704a7
commit 652fb393a3
15 changed files with 15 additions and 1 deletions
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -3,6 +3,7 @@ package rocket
 import Chisel._
 import uncore._
 import Util._
+import cde.{Parameters, Field}

 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
  val outerDataBeats = p(TLKey(p(TLId))).dataBeats