187 lines
7.9 KiB
Scala
187 lines
7.9 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import diplomacy._
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import scala.collection.mutable.ListBuffer
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
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def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu)
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def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
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}
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def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
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require (!ei.isEmpty)
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Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_))))
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}
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var emitMonitors = true
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var stressTestDecoupled = false
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var combinationalCheck = false
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def colour = "#000000" // black
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def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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val monitor = if (emitMonitors) {
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Some(LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)))
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} else {
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None
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}
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(monitor, () => {
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bi <> bo
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monitor.foreach { _.module.io.in := TLBundleSnoop(bo) }
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if (combinationalCheck) {
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// It is forbidden for valid to depend on ready in TL2
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// If someone did that, then this will create a detectable combinational loop
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bo.a.ready := bi.a.ready && bo.a.valid
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bi.b.ready := bo.b.ready && bi.b.valid
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bo.c.ready := bi.c.ready && bo.c.valid
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bi.d.ready := bo.d.ready && bi.d.valid
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bo.e.ready := bi.e.ready && bo.e.valid
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}
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if (stressTestDecoupled) {
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// Randomly stall the transfers
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val allow = LFSRNoiseMaker(5)
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bi.a.valid := bo.a.valid && allow(0)
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bo.a.ready := bi.a.ready && allow(0)
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bo.b.valid := bi.b.valid && allow(1)
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bi.b.ready := bo.b.ready && allow(1)
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bi.c.valid := bo.c.valid && allow(2)
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bo.c.ready := bi.c.ready && allow(2)
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bo.d.valid := bi.d.valid && allow(3)
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bi.d.ready := bo.d.ready && allow(3)
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bi.e.valid := bo.e.valid && allow(4)
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bo.e.ready := bi.e.ready && allow(4)
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// Inject garbage whenever not valid
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val bits_a = bo.a.bits.fromBits(LFSRNoiseMaker(bo.a.bits.asUInt.getWidth))
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val bits_b = bi.b.bits.fromBits(LFSRNoiseMaker(bi.b.bits.asUInt.getWidth))
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val bits_c = bo.c.bits.fromBits(LFSRNoiseMaker(bo.c.bits.asUInt.getWidth))
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val bits_d = bi.d.bits.fromBits(LFSRNoiseMaker(bi.d.bits.asUInt.getWidth))
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val bits_e = bo.e.bits.fromBits(LFSRNoiseMaker(bo.e.bits.asUInt.getWidth))
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when (!bi.a.valid) { bi.a.bits := bits_a }
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when (!bo.b.valid) { bo.b.bits := bits_b }
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when (!bi.c.valid) { bi.c.bits := bits_c }
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when (!bo.d.valid) { bo.d.bits := bits_d }
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when (!bi.e.valid) { bi.e.bits := bits_e }
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}
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})
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}
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override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLClientPortParameters =
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pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
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override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLManagerPortParameters =
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pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) })
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override def getO(pu: TLManagerPortParameters): Option[BaseNode] = {
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val head = pu.managers.map(_.nodePath.headOption)
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if (head.exists(!_.isDefined) || head.map(_.get).distinct.size != 1) {
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None
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} else {
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val subproblem = pu.copy(managers = pu.managers.map(m => m.copy(nodePath = m.nodePath.tail)))
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getO(subproblem) match {
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case Some(x) => Some(x)
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case None => Some(head(0).get)
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}
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}
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}
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}
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// Nodes implemented inside modules
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case class TLIdentityNode() extends IdentityNode(TLImp)
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case class TLClientNode(portParams: TLClientPortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SourceNode(TLImp)(portParams, numPorts)
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case class TLManagerNode(portParams: TLManagerPortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SinkNode(TLImp)(portParams, numPorts)
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object TLClientNode
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{
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def apply(params: TLClientParameters) =
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new TLClientNode(TLClientPortParameters(Seq(params)), 1 to 1)
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}
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object TLManagerNode
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{
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def apply(beatBytes: Int, params: TLManagerParameters) =
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new TLManagerNode(TLManagerPortParameters(Seq(params), beatBytes, 0), 1 to 1)
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}
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case class TLAdapterNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
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// Nodes passed from an inner module
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case class TLOutputNode() extends OutputNode(TLImp)
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case class TLInputNode() extends InputNode(TLImp)
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// Nodes used for external ports
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case class TLBlindOutputNode(portParams: TLManagerPortParameters) extends BlindOutputNode(TLImp)(portParams)
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case class TLBlindInputNode(portParams: TLClientPortParameters) extends BlindInputNode(TLImp)(portParams)
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/** Synthesizeable unit tests */
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import unittest._
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class TLInputNodeTest extends UnitTest(500000) {
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class Acceptor extends LazyModule {
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val node = TLInputNode()
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val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
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tlram.node := node
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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}
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}
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val fuzzer = LazyModule(new TLFuzzer(5000))
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LazyModule(new Acceptor).node := TLFragmenter(4, 64)(fuzzer.node)
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io.finished := Module(fuzzer.module).io.finished
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}
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object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncEdgeParameters, TLAsyncBundle]
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{
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def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
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def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
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def bundleO(eo: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = {
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require (eo.size == 1)
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Vec(eo.size, new TLAsyncBundle(eo(0).bundle))
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}
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def bundleI(ei: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = {
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require (ei.size == 1)
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Vec(ei.size, new TLAsyncBundle(ei(0).bundle))
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}
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def colour = "#ff0000" // red
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def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => { bi <> bo })
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}
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override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
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pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
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override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
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pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
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}
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case class TLAsyncIdentityNode() extends IdentityNode(TLAsyncImp)
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case class TLAsyncOutputNode() extends OutputNode(TLAsyncImp)
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case class TLAsyncInputNode() extends InputNode(TLAsyncImp)
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case class TLAsyncSourceNode() extends MixedNode(TLImp, TLAsyncImp)(
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dFn = { case (1, s) => s.map(TLAsyncClientPortParameters(_)) },
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uFn = { case (1, s) => s.map(_.base) },
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numPO = 1 to 1,
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numPI = 1 to 1)
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case class TLAsyncSinkNode(depth: Int) extends MixedNode(TLAsyncImp, TLImp)(
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dFn = { case (1, s) => s.map(_.base) },
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uFn = { case (1, s) => s.map(TLAsyncManagerPortParameters(depth, _)) },
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numPO = 1 to 1,
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numPI = 1 to 1)
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